shell.albert
Member level 4
Hi friends,
I meet a serious problem.My company got a ISA bus data acquisition card.My task is to develop a PC based control and analysis software.But the seller only can supply the communication protocol.No I/O address.No Test Program.
From the schematics,I know the card only use A9~A1 9bit address,so the address range is 0x000~0x3FE, the address range is so wide.
What should I do ? How can I know the register address, I/O address?
Come on ,help me!
Help me!!!
---------- Post added at 02:39 ---------- Previous post was at 02:30 ----------
No good sleep last night,I got three method,as following:
1.Write a test program under dos using inport() outport() function,scan and read all the port in address range 0x000~0x3FE.
According the read result to adjust the port address.If zero returned,this port must not be.If non-zero returned,this port is maybe a valid I/O address.
2.Thanks to the ISA logical is implemented by FPGA from Altera.From the schematics,no decoder logic can be found.So why not reverse the FPGA souce code,convert the program file(binary,hex) to VHDL/Verilog HDL code to see the detail of decode logical.
3.So far, no idea.
I meet a serious problem.My company got a ISA bus data acquisition card.My task is to develop a PC based control and analysis software.But the seller only can supply the communication protocol.No I/O address.No Test Program.
From the schematics,I know the card only use A9~A1 9bit address,so the address range is 0x000~0x3FE, the address range is so wide.
What should I do ? How can I know the register address, I/O address?
Come on ,help me!
Help me!!!
---------- Post added at 02:39 ---------- Previous post was at 02:30 ----------
No good sleep last night,I got three method,as following:
1.Write a test program under dos using inport() outport() function,scan and read all the port in address range 0x000~0x3FE.
According the read result to adjust the port address.If zero returned,this port must not be.If non-zero returned,this port is maybe a valid I/O address.
2.Thanks to the ISA logical is implemented by FPGA from Altera.From the schematics,no decoder logic can be found.So why not reverse the FPGA souce code,convert the program file(binary,hex) to VHDL/Verilog HDL code to see the detail of decode logical.
3.So far, no idea.
