[SOLVED] [HELP] Low power VLSI design using Variable Body Biasing (VBB)Techniques

Anyone know about low power VLSI design using Variable Body Biasing Techniques to reduce static power consumption? Can someone discuss on it?

the information i found on this is it correct?
http://www.eeherald.com/section/design-guide/Low-Power-VLSI-Design.html

Hello,

VBB can very useful for tuning transistors in low power applications. With VBB, you are effectively you are tuning the threshold voltage of the transistor by applying voltage to the bulk. If you want low leakage (e.g. at low frequencies or in devices where leakage is a problem) then you need to use VBB to increase the threshold voltage.

However, VBB is not very effective in modern CMOS (e.g. below 130nm). If you are really looking for a VBB that can help you with leakage, definitely take a look at FD-SOI (fully-depleted silicon-on-insulator). FD-SOI has VBB, also called back-gate biasing, that allows for a huge tuning range of the threshold voltage. A great overview of this technology can be found here (open source paper):
https://www.mdpi.com/2079-9268/4/3/168

Good luck and I hope this info helps!

Cheers,
analogLow