Adnan86
Full Member level 2
Hi, I write below code for single cycle MIPS, base on chapter 7 of Harris book(Digital design ...).
I used ISE 14.7 for simulation.
I just want use data in memory and show result in simulation.
but after simulate it , all out put show unknown " X " in output.
i will appreciate if some one give me some help.
thanks
- - - Updated - - -
imem, rg , dmem
its just have some number in hex.
- - - Updated - - -
and save them in project
I used ISE 14.7 for simulation.
I just want use data in memory and show result in simulation.
but after simulate it , all out put show unknown " X " in output.
i will appreciate if some one give me some help.
thanks
Code:
// ---- Adder
module adder( input [31:0] datain1, datain2,
output[31:0] dataout);
assign dataout = datain1 + datain2;
endmodule
//--------------------------------------
// ---- ALU
module alu (input [31:0] srca, srcb,
input [2:0] alucontrol,
output reg [31:0] aluresult,
output reg zero );
always @(alucontrol, srcb, srca)
begin
case (alucontrol)
3'b010 : //add
begin
aluresult = srca + srcb ;
zero = 0 ;
end
3'b000 : //and
begin
aluresult = srca & srcb ;
zero = 0 ;
end
3'b001 : //or
begin
aluresult = srca | srcb ;
zero = 0 ;
end
3'b110 : //subtract
begin
aluresult = srca - srcb ;
if (aluresult == 0)
zero = 1 ;
else zero = 0 ;
end
3'b111 : //slt
begin
aluresult = srca - srcb ;
if ({aluresult[31]} == 1)
begin
aluresult = 1 ;
zero = 0 ;
end
else if (aluresult[31] == 0)
zero = 1 ;
else
begin
zero = 0 ;
aluresult = 0 ;
end
end
default : zero = 0 ;
endcase
end
endmodule
// --------------------------------------
// ---- Alu Decoder of Control Unit
module aludecoder (input [5:0] funct,
input [1:0] aluop,
output reg [2:0] alucontrol);
always @(aluop, funct)
begin
if(aluop == 2'b00)
begin
alucontrol <= 3'b010 ; //add
end
else if(aluop == 2'b01)
begin
alucontrol <= 3'b110 ; //substract
end
else if(aluop == 2'b10 || aluop == 2'b11)
begin
case (funct)
6'b100000 : alucontrol <= 3'b010; //add
6'b100010 : alucontrol <= 3'b110; //subtract
6'b100100 : alucontrol <= 3'b000; //and
6'b100101 : alucontrol <= 3'b001; //or
6'b101010 : alucontrol <= 3'b111; //slt
default : alucontrol <= 3'b001; //default
endcase
end
end
endmodule
// --------------------------------------
// ---- Main Decoder of Control Unit
module maindecoder (input [5:0] opcode,
output [1:0] aluop,
output memtoreg, memwrite, branch,
output alusrc, regdst, regwrite);
reg [7:0] maindec;
assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg,
aluop} = maindec ;
always @(opcode)
case (opcode)
6'b000000 : maindec <= 8'b11000010 ; //R-type
6'b100011 : maindec <= 8'b10100100 ; // lw
6'b101011 : maindec <= 8'b00101000 ; // sw
6'b000100 : maindec <= 8'b00010001 ; // beq
default : maindec <= 8'b00000000; //default
endcase
endmodule
// ----------------------------------------
// ---- Control Unit with combination of Main Decoder and Alu Decoder
module controlunit (input [5:0] opcode, funct,
input zero,
output [2:0] alucontrol,
output memtoreg, memwrite, pcsrc,
output alusrc, regdst, regwrite);
wire branch ;
wire [1:0] aluop ;
maindecoder memdec1 (opcode,aluop,memtoreg, memwrite, branch,
alusrc, regdst, regwrite);
aludecoder aludec1 ( funct, aluop, alucontrol);
assign pcsrc = branch & zero ;
endmodule
// ----------------------------------------
// ---- Data Memory
module datamem (input clk, we,
input [31:0] a, wd,
output reg [31:0] rd);
//(* ram_init_file = "dmem1.mif" *)reg [31:0] dmem[63:0];
reg [31:0] dmem[63:0];
always @(we)
begin
if(we==0)
rd <= dmem[a];
end
always @ (posedge clk)
begin
if (we)
dmem[a] <= wd;
end
//assign rd = dmem[a[31:0]];
initial $readmemh ("dmem.dat", dmem);
endmodule
//-------------------------------------
// ---- PC counter
module pc_counter (input clk,
input [31:0] in,
output reg [31:0] out);
always @ (posedge clk )
begin
out <= in ;
end
endmodule
//---------------------------------------
// ---- Instrution Memory
module instrmemory(input[31:0] a,
output reg [31:0] rd);
//(* ram_init_file = "imem1.mif" *) reg[31:0] imem[63:0];
reg[31:0] imem[63:0];
always @ (a)
begin
rd <= imem[a];
end
initial $readmemh ("imem.dat", imem);
endmodule
//----------------------------------
//---- MUX
/*module mux (input [31:0]i0, i1,
input s,
output e);
assign e = (s!=0) ? i1 : i0 ;
endmodule*/
//---- 5 bits
module mux_5 (i0, i1, s, e);
input [4:0]i0;
input [4:0]i1;
input s;
output [4:0]e;
assign e = (s!=0) ? i1 : i0 ;
endmodule
//---- 32 bits
module mux_32 (i0, i1,s,e);
input [31:0]i0;
input [31:0]i1;
input s;
output [31:0]e;
assign e = (s!=0) ? i1 : i0 ;
endmodule
//------------------------------
// ---- Register File
module registerfile (input clk,
input we3,
input [4:0] ra1, ra2, wa3,
input [31:0] wd3,
output [31:0] rd1, rd2);
//(* ram_init_file = "regfile1.mif" *) reg [31:0] rg[31:0];
reg [31:0] rg[31:0];
always @ (posedge clk)
begin
if (we3)
rg[wa3] <= wd3;
end
assign rd2=rg[ra2];
assign rd1=rg[ra1];
initial $readmemh ("rg.dat", rg);
endmodule
//----------------------------
// ---- Shift to Left by 2 bit
module shiftleft2 (input [31:0] a,
output [31:0] b);
assign b = {a[29:0],2'b00} ;
endmodule
//----------------------------
// ---- Sign Extend
module signextend (input [15:0] x,
output [31:0] y);
assign y = {{16{x[15]}}, x } ;
endmodule
//-----------------------------
// ---- MIPS
module MIPS (input clk,
output [31:0] instr, result, srca, srcb, aluresult ,
output [2:0] alucontrol);
wire memtoreg, memwrite, branch, alusrc,
zero, pcsrc, regdst, regwrite ;
wire [4:0] writereg ;
wire [31:0] pcplus4, signimm, signimmshift2, writedata, pc, nextpc;
wire [31:0] readdata, pcbranch ;
// pc counter
pc_counter pc_counter1 ( clk, nextpc, pc);
adder addplus4 (pc , 32'd4, pcplus4);
shiftleft2 signshift ( signimm, signimmshift2);
adder pcbranch1 (signimmshift2 , pcplus4, pcbranch);
mux_32 mux1 ( pcplus4, pcbranch, pcsrc, nextpc);
// instruction memory
instrmemory insmem(pc, instr);
//register file
registerfile regfile1 ( clk, regwrite,instr[25:21], instr[20:16],
writereg, result, srca, writedata);
mux_5 mux2 ( instr[20:16], instr[15:11], regdst, writereg);
mux_32 mux3 ( aluresult, readdata, memtoreg, result);
signextend signext1 (instr[15:0], signimm);
alu alu1 (srca, srcb, alucontrol, aluresult, zero );
mux_32 mux4 ( writedata, signimm, alusrc, srcb);
//control unit
controlunit ctrl1 (instr[31:26], instr[5:0], zero, alucontrol,
memtoreg, memwrite, pcsrc, alusrc, regdst, regwrite);
//data memory
datamem dm1 (clk , memwrite, aluresult, writedata, readdata );
endmodule
- - - Updated - - -
imem, rg , dmem
its just have some number in hex.
- - - Updated - - -
and save them in project