Re: Help in Verilog coding
Hi,
The value of SD_INIT_START_SEQ_LEN depends on the value of SIM_COMPILE. When SIM_COMPILE is 1, SD_INIT_START_SEQ_LEN has the value 3, otherwise a0. Looking at the name, for synthesis the value is a0. I guess this mechanism is used to shorten the simulation time. When there is documentation available you should find it somewhere in it.
The file spiMaster_defines.v is a so called include file. In this file you can define default values. In this case the default values depends on another variable to create a flexible design.
Devas