max tran violation means a maximum transition time violation on any pin. it doesn't have to be on the clock tree cells, it can happen on any cell. there are two reasons why max tran violations appear:
1) your standard cells are characterised to work in a certain range. a max tran violation might indicate that a cell is working outside its characterization range and therefore the tool had to guess its timing by extrapolating. this is not good, but won't necessarily kill the chip.
2) the designer sets a max tran target that is more strict than the default from the std cell library. this is typically used to help with high-speed designs so all signals transition faster and are less susceptible to glitches/coupling. a violation of this kind could have an impact on closure and make the design time increase.