Hi.all,
I need to desgin an opamp to buffer my output voltage and to drive the load (10pf and 5K ohm),the buffer opamp seemed very tough for me:
1 3.3v power supply,0.18 cmos technology
2 0.2-1.6v input and output common mode range
3 when drive the load 9bit settling time is 1us from 0.5 to 1.5v
Pls give me some advice on the OP design or give me some kind of structure or some paper on the design of this kind of OP .
Hi,vbhupendra
my plan is to use an pmos folded cascode with a source follower,the 1st pole(pole of first stage) is dominant pole,and source follower has the 2nd pole.from the settling time requirement,the bandwith of the OP is at least 6MHz,and the cap load and res load with reduce the bandwith and eat up the phase margin,this will greatly reduce the performance of the OP,don't you think so?