hello frndz,
i hav a verilog code which i want to encrypt using Modelsim so that the final file is in the format such as "1010.." so that the user doesnt know wht the code is but is successful in using the file in his application.
There are several options with varying levels of protection:
1. Use `protect/`endprotect, then tools like Modelsim/VCS/NC can encrypt them.
2. Ship compiled library such as "work" in Modelsim. The downside is end user is restricted to same tool chain and may be even versions.
3. Use special IP encryption that comes with your tool such as "-nodebug" with Modelsim (Look in their doc for more), gen_ip in VCS etc.
4. Use specialized tool such as Synopsys's VMC. My team has lot of experience in this especially with SystemVerilog.