Okay, here's my complete Main program and TestBench
The Filter,Filter2 and DDS is generated from CoreGen
***Main Program***
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DownConverter is
Port ( m_clk,res : in STD_LOGIC; --Master Clock & Reset
X : in STD_LOGIC_VECTOR(9 downto 0); --10bit Input
Xr2,Xi2 : out STD_LOGIC_VECTOR(9 downto 0); --10bit Output
It2,Qt2 : out STD_LOGIC_VECTOR(26 downto 0) --27bit Output
);
end DownConverter;
architecture main OF DownConverter is
type state is (Start,S1,S2,S3,S4);
Signal Current_state,Next_state : State;
Signal Xr2i,Xi2i : STD_LOGIC_VECTOR(9 downto 0); --Internal Signal for DC
Signal sclr,clk : STD_LOGIC;
Signal rfd,rdy,nd: STD_LOGIC;
Signal dout,dout2: STD_LOGIC_VECTOR(26 downto 0);
Signal din,din2 : STD_LOGIC_VECTOR(9 downto 0);
-----------------------------------------------------------------------------------
--------------------------- Declare Component <Filter1> ---------------------------
Component filter is
port (
sclr : in STD_LOGIC;
rfd : out STD_LOGIC;
rdy : out STD_LOGIC;
nd : in STD_LOGIC := '1';
clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 26 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end Component;
----------------------------------------------------------------------------------
-------------------------- Declare Component <Filter2> ---------------------------
Component filter2 is
port (
sclr : in STD_LOGIC;
rfd : out STD_LOGIC;
rdy : out STD_LOGIC;
nd : in STD_LOGIC := '1';
clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 26 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end Component;
----------------------------------------------------------------------------------
begin
-------------------- Component Instantiation Filter 1 --------------------
u2:component Filter Port Map (din=>din,
dout=>dout,
clk=>m_clk,
sclr=>res,
rfd=>rfd,
rdy=>rdy,
nd=>nd
);
--------------------------------------------------------------------------
-------------------- Component Instantiation Filter 2 --------------------
u3:component Filter2 Port Map (din=>din2,
dout=>dout2,
clk=>m_clk,
sclr=>res,
rfd=>rfd,
rdy=>rdy,
nd=>nd
);
--------------------------------------------------------------------------
process ( m_clk,res )
begin
if res='1' then
Current_state <= Start;
elsif (m_clk'event and m_clk='1') then
Current_state <= Next_state;
end if;
end process;
process ( Current_state,X )
begin
case Current_state is
when Start=> Next_state <= S1;
Xr2i<= X ; Xi2i<= "0000000000";
when S1 => Next_state <= S2;
Xr2i<= "0000000000" ; Xi2i<= 0-X;
when S2 => Next_state <= S3;
Xr2i<= 0-X ; Xi2i<= "0000000000";
when S3 => Next_state <= S4;
Xr2i<= "0000000000" ; Xi2i<= X;
when S4 => Next_State <= S1;
Xr2i<= X ; Xi2i<= "0000000000";
end case;
end process;
nd<= '1';
sclr<=res;
Xr2<=Xr2i;
Xi2<=Xi2i;
Din<=Xr2i;
Din2<=Xi2i;
It2<=Dout;
Qt2<=Dout2;
end;
***TestBench***
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_textio.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
-- Entity
ENTITY DownTB IS
END;
-- Architecture
ARCHITECTURE TB OF DownTB IS
-- Component Declaration
---------------- Declare Component <Down Converter>-----------------------------
COMPONENT DownConverter
PORT(
m_clk : IN std_logic; -- Master Clock
res : IN std_logic; -- Master Reset
X : IN std_logic_vector(9 downto 0); -- Input
It2,Qt2 : OUT STD_LOGIC_VECTOR(26 downto 0); -- 27bit Output
Xr2,Xi2 : OUT std_logic_vector(9 downto 0) -- 10bit Output
);
END COMPONENT;
--------------------------------------------------------------------------------
---------------- Declare Component <Direct Digital Synthesizer>-----------------
COMPONENT dds IS
PORT (
clk : IN STD_LOGIC;
sclr : IN STD_LOGIC;
rfd : OUT STD_LOGIC;
rdy : OUT STD_LOGIC;
Sine : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
--------------------------------------------------------------------------------
-- For u1: DownConverter use entity work.DownConverter(Main);
SIGNAL m_clk : std_logic:='1'; -- Master Clock
SIGNAL d_clk : std_logic:='1'; -- DDS Clock Rate at 500MHz
SIGNAL res : std_logic:='1'; -- Master Reset
SIGNAL X : std_logic_vector(9 downto 0);
SIGNAL Xr2,Xi2 : std_logic_vector(9 downto 0);
SIGNAL Sine : std_logic_vector(9 downto 0);
SIGNAL It2,Qt2 : std_logic_vector(26 downto 0);
SIGNAL rfd,rdy : std_logic;
BEGIN
----------------- Component Instantiation Down Converter -----------------
u1: DownConverter PORT MAP(m_clk=>m_clk,
res=>res,
X=>X,
Xr2=>Xr2,
Xi2=>Xi2,
It2=>It2,
Qt2=>Qt2
);
--------------------------------------------------------------------------
----------- Component Instantiation Direct Digital Synthesizer -----------
u4: dds PORT MAP (clk=>d_clk,
sclr=>res,
rdy=>rdy,
rfd=>rfd,
Sine=>Sine
);
--------------------------------------------------------------------------
X <= Sine;
res <= '1','0' after 0.1 ns;
m_clk <= not m_clk after 1 ns; --Master Clock
d_clk <= not d_clk after 1 ns; --DDS Clock
end;
Added after 9 minutes:
This is the coe File that both my filter use.
This is the Full Specification i used for my DDS
DDS CoreGen Spec :
Function : Sine
DSS Clock Rate : 500MHz
Spurious Free Dynamic Range : 60
Frequency Resolution : 0.1165
Output Frequency : 120MHz-125Mhz (Fixed)
Phase Offset Angel : 0.0 (Fixed)
SClr Pin Enabled
Noise Shaping : Auto
Memory Type : Auto
Rdy and Rfd Pins Enabled
Pipelined Enabled
Accumulator Latency : One Cycle