module M_MAX (rst,clk,Adc6,m_max);
//============ parameter declared ==================
parameter ADC_min = 12'd2184;
//parameter ADC_min_t = 16'd2200;
parameter num = 18; // 4095 * 64 =262080 => 18 bit
parameter average_done = 7'd64; // 64 +28; div letency 28
parameter Xbit = 5'd24;
parameter Mbit = 4'd12;
//===================================================
input clk, rst;
input [11:0]Adc6 ;
output [Xbit-1:0] m_max;
//================= wire declared =================
wire [Mbit-1:0] m1_f,m1_i;
wire rfd;
wire [11:0] feedback_v1;
wire [Xbit-1:0] m_max;
//================ reg declared ===================
reg [num-1:0] feedback_v_tmp;
reg [6:0] cnt;
reg [Xbit-1:0] m_max_tmp;
reg [Xbit-1:0] m_old_f;
reg [11:0] cnt_tri;
reg [11:0] m_old_i;
//reg [11:0] Adc_tmp;
//reg [11:0] Adc[0:63];
//===================================================
//initial $readmemb (`code_in2, Adc);
assign feedback_v1 = feedback_v_tmp >>6 ;
DIV_12x12_FRA U1(.rfd(rfd), .clk(clk), .dividend(ADC_min), .quotient(m1_i), .divisor(feedback_v1), .fractional(m1_f));
assign m_max = m_max_tmp;
always@(posedge clk)
begin
if(rst)
begin
cnt_tri <= 12'd0;
cnt <= 7'd0;
feedback_v_tmp <= 18'd0;
end
else
begin
cnt_tri <= cnt_tri+1'b1;
if(cnt_tri == 12'd2666)
begin
feedback_v_tmp <= feedback_v_tmp +Adc6;
cnt <= cnt+1'b1;
cnt_tri <= 12'd0;
//Adc_tmp <= Adc[cnt+1];
end
else
begin
if (cnt == average_done)
begin
cnt <= 7'd0;
end
end
end
end
always@(posedge clk)
begin
if(rst)
begin
m_max_tmp <= 24'd0;
m_old_f <= 12'hCCC;
m_old_i <= 12'd0;
end
else
begin
if(cnt == average_done)
begin
m_max_tmp <= ({2'd0,m1_i,10'd0} + {4'd0,m1_i,8'd0} + {7'd0,m1_i,5'd0} + {8'd0,m1_i,4'd0} + {10'd0,m1_i,2'd0}+ {12'd0,m1_i}
+{2'd0,m1_f,10'd0} + {4'd0,m1_f,8'd0} + {7'd0,m1_f,5'd0} + {8'd0,m1_f,4'd0} + {10'd0,m1_f,2'd0} + {12'd0,m1_f});
m_old_f <= m1_f;
m_old_i <= m1_i;
end
else
begin
m_max_tmp <= ({2'd0,m_old_i,10'd0} + {4'd0,m_old_i,8'd0} + {7'd0,m_old_i,5'd0} + {8'd0,m_old_i,4'd0} + {10'd0,m_old_i,2'd0} + {12'd0,m_old_i}
+{2'd0,m_old_f,10'd0} + {4'd0,m_old_f,8'd0} + {7'd0,m_old_f,5'd0} + {8'd0,m_old_f,4'd0} + {10'd0,m_old_f,2'd0} + {12'd0,m_old_f});
m_old_f <= m_old_f;
m_old_i <= m_old_i;
end
end
end
endmodule