Hi,TiwstedNeurons
For a 10bit 80M adc. How about if I caculate the settling time limitation in this way(assume half-cycle ):
2^10=1024 ---> 1/(2fs)<7tau -----> tau< 1/(14fs) ------> tau< 3.57 ns
So would you please let me know how you get 5.5 ns? thx
1. 5.5ns is not calculated by me, it is the simulation result from my nonoverlap clock circuit,it is just a example,not a exact value.just as wan said:"5.5ns is not a exact value for settling time, simon110 want to say settling time should be less than ts/2(6.25n). Excluding falling and rising time and nonoverlap time, we can set a 5.5ns settling time."
2.
a. for a 10bit 80M adc, at first, you should ensure the total error of SHA below 1/2 LSB i.e. 1/2^11.
b. if you adopt the flip around SHA, the total error includes the error caused by finite gain and GBW; if your choose the charge transfer sha , the total error should also include capacitor mismatch.
c. if the configuration(flip around or charge transfer) is chosen, you should allocate the error between the two(or three)factors.
d. then you can calculate the specification.
Added after 44 minutes:
Hi wan
1. you said your sampling rate is 40MSps, so the input signal fre. should below 20MHz, so if your input fre. is 51MHz, the spectrum will overlapp each other, the sharp drop of SINAD is inevitable.
2. you said "And larger the input frequency, the differnce of input value and corresponding output value became lager, especailly at max slope of Sin input wave. Is it right,and why? I think jitter is not the reason because i tried with a deal clk generator. "
I think the phenomena is natural. my reasons are below:
a. the gain of your op amp is finite and dependent on the input fre. A is A(f), not a constant!!! when the input fre. become larger, the gain of your op amp will decrease, so the static error of SHA increase, the differnce of input value and corresponding output value became larger.
b. the GBW of your op amp is finite, when your input signal increase, the op amp will respond slowly, it is inevitable. at max slope of Sin input wave,the input vary fast most , the speed of your op amp will be slowest!
in a word, it is the finite gain and finite GBW that cause the phenomna!
My advices:
as long as the differnce between the input value and corresponding output value is in the range of your error bound at the worst situation, the phenomna is acceptable.
worst situation: input frequency=fsample/2 and at max slope of Sin input wave.