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Help:how to evaluate the performance of SHA in ADC?

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wan

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Hello, everybody. I have a question for help: When i design a sample/hold circuit, I want to know how to evaluate the performance.
SHA is a critical component. I think I should do trans simulation and take fft. Is it ok? In general, for 10bit adc, what is the spec that SHA should achieve?
Expect your reply and thanks in advance.
 

wued

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using pss/pac in spectreRF
 

simon110

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you can do trans simulation and take fft.
when you do trans simulation, you can find some information such as settling time.for example, a 10bit 80M pipeline adc, the settling time should be not more than 5.5ns(exclude the nonoverlap time), as for the dynamic specification, the most important is SNDR and SFDR. in order to get the ENOB beyond 10bit, the SNDR>62dB even if the frequency =fsample/2
 

ezt

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Hi wan,
You should use a transient analysis and move the results to MATLAB or any other software suitable for math calculations (I always prefer using MATLAB). Then there you can perform FFT function and find SFDR and SNDR of your S/H front-end stage. Since this stage is the front-end of the whole system so its performance should be better than the performance of the whole structure, otherwise the performance of ADC would be degraded.
As simon110 said, the settling time is important. It should settle in less than a half-cycle (Ts/2). On the other hand, due to error limitations, since it's the first stage and if we assume that its feedback factor is near "1" (which is usually not exactly 1 and hence the dc-gain should be larger), the DC-gain of SHA should be larger than 2^10 (about 60dB).
Don't forget the input of your ADC is the output of front-end SHA. Hence, the better front-end S/H stage, the better your whole ADC performance!

Regards,
EZT
 

    wan

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TiwstedNeurons

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Hi,Simon110

For a 10bit 80M adc. How about if I caculate the settling time limitation in this way(assume half-cycle ):

2^10=1024 ---> 1/(2fs)<7tau -----> tau< 1/(14fs) ------> tau< 3.57 ns

So would you please let me know how you get 5.5 ns? thx
 

wan

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Thanks, ezt and simon110
I did trans simulation with different input frequency,and took fft with matlab. I got the SINAD of 79.8dB at Nyquist rate (sampling rate is 40MSps), that correpond to 13ENOB. When i increased the input frequency to 51MHz, I found that the SINAD droped to 67dB(11ENOB). I am confused why SINAD droped so.
And larger the input frequency, the differnce of input value and corresponding output value became lager, especailly at max slope of Sin input wave. Is it right,and why? I think jitter is not the reason because i tried with a deal clk generator.

TiwstedNeurons, "5.5ns" is not a exact value for settling time, simon110 want to say settling time should be less than ts/2(6.25n). Excluding falling and rising time and nonoverlap time, we can set a 5.5ns settling time.
 

simon110

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Hi,TiwstedNeurons
For a 10bit 80M adc. How about if I caculate the settling time limitation in this way(assume half-cycle ):

2^10=1024 ---> 1/(2fs)<7tau -----> tau< 1/(14fs) ------> tau< 3.57 ns

So would you please let me know how you get 5.5 ns? thx

1. 5.5ns is not calculated by me, it is the simulation result from my nonoverlap clock circuit,it is just a example,not a exact value.just as wan said:"5.5ns is not a exact value for settling time, simon110 want to say settling time should be less than ts/2(6.25n). Excluding falling and rising time and nonoverlap time, we can set a 5.5ns settling time."

2.
a. for a 10bit 80M adc, at first, you should ensure the total error of SHA below 1/2 LSB i.e. 1/2^11.
b. if you adopt the flip around SHA, the total error includes the error caused by finite gain and GBW; if your choose the charge transfer sha , the total error should also include capacitor mismatch.
c. if the configuration(flip around or charge transfer) is chosen, you should allocate the error between the two(or three)factors.
d. then you can calculate the specification.

Added after 44 minutes:

Hi wan

1. you said your sampling rate is 40MSps, so the input signal fre. should below 20MHz, so if your input fre. is 51MHz, the spectrum will overlapp each other, the sharp drop of SINAD is inevitable.

2. you said "And larger the input frequency, the differnce of input value and corresponding output value became lager, especailly at max slope of Sin input wave. Is it right,and why? I think jitter is not the reason because i tried with a deal clk generator. "

I think the phenomena is natural. my reasons are below:

a. the gain of your op amp is finite and dependent on the input fre. A is A(f), not a constant!!! when the input fre. become larger, the gain of your op amp will decrease, so the static error of SHA increase, the differnce of input value and corresponding output value became larger.

b. the GBW of your op amp is finite, when your input signal increase, the op amp will respond slowly, it is inevitable. at max slope of Sin input wave,the input vary fast most , the speed of your op amp will be slowest!

in a word, it is the finite gain and finite GBW that cause the phenomna!

My advices:
as long as the differnce between the input value and corresponding output value is in the range of your error bound at the worst situation, the phenomna is acceptable.

worst situation: input frequency=fsample/2 and at max slope of Sin input wave.
 

    wan

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wan

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Thank simon110 very much for your help. I have other questions.
/1. you said your sampling rate is 40MSps, so the input signal fre. should below 20MHz, so if your input fre. is 51MHz, the spectrum will overlapp each other, the sharp drop of SINAD is inevitable./

You are right, the spectrum will overlapp when input frequency exceed Nyquist frequency. But, SINAD of a well-designed ADC will drop slowly even when input frequecy exceed. We can see that in some papers and PHD thesis from UCB.

//I think the phenomena is natural. my reasons are below:

a. the gain of your op amp is finite and dependent on the input fre. A is A(f), not a constant!!! when the input fre. become larger, the gain of your op amp will decrease, so the static error of SHA increase, the differnce of input value and corresponding output value became larger. /

Dc gain of OTA in THA is 90dB. At 10MHz input, open loop gain drops to 50dB. If we calculate gain error of 1/Aβ, It is clear that 50dB is too small for the gain error. The sampling rate is constant 40Msps, the values given to the opamp is at a fixed rate even when signal frequency increases. And "A" in gain error 1/Aβ is always dc gain value?

//My advices:
as long as the differnce between the input value and corresponding output value is in the range of your error bound at the worst situation, the phenomna is acceptable.
worst situation: input frequency=fsample/2 and at max slope of Sin input wave. [/quote]//
As you said: in worst situation, the difference between the input value and corresponding output value is less than 1/2LSB? and why 1/2LSB? Thanks!
 

simon110

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Hi wan

1."You are right, the spectrum will overlapp when input frequency exceed Nyquist frequency. But, SINAD of a well-designed ADC will drop slowly even when input frequecy exceed. We can see that in some papers and PHD thesis from UCB"

I think you should examine the SFDR and THD when you simulate your SHA at the input freq. from 20MHz to 51MHz. if you find the SFDR or THD dropping fast and the SNR dropping solwly, then the reason that causes your SINAD dropping fast is the distortion in your SHA rather than the noise.

2."Dc gain of OTA in THA is 90dB. At 10MHz input, open loop gain drops to 50dB. If we calculate gain error of 1/Aβ, It is clear that 50dB is too small for the gain error. The sampling rate is constant 40Msps, the values given to the opamp is at a fixed rate even when signal frequency increases. And "A" in gain error 1/Aβ is always dc gain value?"

In my opinion, I think the "A" in gain error 1/Aβ is not always dc gain value, strictly speaking, the β is also dependent on freq., i.e. β is β(s)


3. "As you said: in worst situation, the difference between the input value and corresponding output value is less than 1/2LSB? and why 1/2LSB? Thanks! "

because the quantization error distribute between ±1/2LSB,if the other error in ADC(include all static error and dynamic ones) is below 1/2LSB, the total error will less than 1LSB,so ADC will give correct digital code.
 

    wan

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