and if i want to give differential clock then how i should use the fpga.
FPGA has output LVDS buffers. Just feed the singal ended clock to the buffer.
i_obufds_clk_d : OBUFDS_LVDS_25
port map(O => S3_TxClk_p, OB => S3_TxClk_n, I => asi_smpte_clk_d);
S3_TxClk_p, S3_TxClk_n are ports and
asi_smpte_clk_d is signal.
and i have to divide the clock according to the requirement of different component on my board.
You can use the DCM(xilinx) or PLL(Altera) indies the FPGA to get the desired clock wiht 50% duty circle. But the number od DCMs are very limited.
You can use T-FlipFlop as avimit suggested. But you will only get 50% duty circle for even divisor, that is 2, 4, 6 .....
It depends on the number of components on ur board. I think 2-4 is OK with FPGA. Use up one or maximum two DCMs.
If the number of componet which require clock is high, you better use clock synthesizer chips. check
**broken link removed**
Added after 17 seconds:
and if i want to give differential clock then how i should use the fpga.
FPGA has output LVDS buffers. Just feed the singal ended clock to the buffer.
i_obufds_clk_d : OBUFDS_LVDS_25
port map(O => S3_TxClk_p, OB => S3_TxClk_n, I => asi_smpte_clk_d);
S3_TxClk_p, S3_TxClk_n are ports and
asi_smpte_clk_d is signal.
and i have to divide the clock according to the requirement of different component on my board.
You can use the DCM(xilinx) or PLL(Altera) indies the FPGA to get the desired clock wiht 50% duty circle. But the number od DCMs are very limited.
You can use T-FlipFlop as avimit suggested. But you will only get 50% duty circle for even divisor, that is 2, 4, 6 .....
It depends on the number of components on ur board. I think 2-4 is OK with FPGA. Use up one or maximum two DCMs.
If the number of componet which require clock is high, you better use clock synthesizer chips. check
**broken link removed**