help fpga design on clock dividing.

[rajsrikanth]

hi everyone

in my project i am using virtex-2 and the actual question is
iam getting clock from the realtime oscillator directly to the fpga

and i have to divide the clock according to the requirement of different component on my board.

and my question is how i should divide the clock in the fpga and can i do that and i have to give the clock to processor and sdram and other components.
pls anybody can give an idea how to divide a clock in the fpga and write the code for dividing the clock

and if i want to give differential clock then how i should use the fpga.

thanks and regards
raj

 

[avimit]

Hi,
Clock division shouldn't be a problem. Use a T-FlipFlop, you get a divide by 2, use another in series, you get a divide by 4 and so on.
For a specific division factor, use a ring-counter, or even a state machine. But here you will have to be carefull about the duty-cycle. If you dont need a 50% duty cycle your problem can eaisly be solved using a ring counter.
Kr,
Avi
http://www.vlsiip.com

 

[JPR75]

You can also use the Digital Clock Manager (DCM), but beware of min / max frequency.

 

[mta97e]

and if i want to give differential clock then how i should use the fpga.

FPGA has output LVDS buffers. Just feed the singal ended clock to the buffer.

i_obufds_clk_d : OBUFDS_LVDS_25
port map(O => S3_TxClk_p, OB => S3_TxClk_n, I => asi_smpte_clk_d);

S3_TxClk_p, S3_TxClk_n are ports and asi_smpte_clk_d is signal.

and i have to divide the clock according to the requirement of different component on my board.

You can use the DCM(xilinx) or PLL(Altera) indies the FPGA to get the desired clock wiht 50% duty circle. But the number od DCMs are very limited.

You can use T-FlipFlop as avimit suggested. But you will only get 50% duty circle for even divisor, that is 2, 4, 6 .....

It depends on the number of components on ur board. I think 2-4 is OK with FPGA. Use up one or maximum two DCMs.
If the number of componet which require clock is high, you better use clock synthesizer chips. check **broken link removed**

Added after 17 seconds:

and if i want to give differential clock then how i should use the fpga.

FPGA has output LVDS buffers. Just feed the singal ended clock to the buffer.

i_obufds_clk_d : OBUFDS_LVDS_25
port map(O => S3_TxClk_p, OB => S3_TxClk_n, I => asi_smpte_clk_d);

S3_TxClk_p, S3_TxClk_n are ports and asi_smpte_clk_d is signal.

and i have to divide the clock according to the requirement of different component on my board.

You can use the DCM(xilinx) or PLL(Altera) indies the FPGA to get the desired clock wiht 50% duty circle. But the number od DCMs are very limited.

You can use T-FlipFlop as avimit suggested. But you will only get 50% duty circle for even divisor, that is 2, 4, 6 .....

It depends on the number of components on ur board. I think 2-4 is OK with FPGA. Use up one or maximum two DCMs.
If the number of componet which require clock is high, you better use clock synthesizer chips. check **broken link removed**

 

[maizic]

I am sure the virtex-2 will has PLL inside, it is easy to use, just see a few pages document

 

[JPR75]

I am sure the virtex-2 will has PLL inside, it is easy to use, just see a few pages document

Not a real PLL, but a Digital Clock Manager (DCM).

 

[rajsrikanth]

thank you for all your suggestions

and i want to know how we can program the DCM, anyone can give some idea.
and how we can generate differential clocks and is it possibel to generate differential clocks

thanks

 

[Alfred_zhang]

DCM is a primitive, u can instantiate it in your code. To learn how it works, read the V2 user guide chapter 3.
Once u generate the clocks(clk_SDRAM) that needed by the other components on the board(SDRAM...), just use it drive a OBUFDS, and the output of this cell will be two differential clocks. u don't have to do anything more. In the v2 user guide, u can find OBUFDS's help too.