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help for vco design!!

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guj1987

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I designed a 2.5GHz CMOS VCO,(core current: 20mA), Rout=300omhs, 3.3V VDD supply, Now core output amplitude is 1~5V. phase noise simulation is about -116dBc/Hz, test is only about -108, the layout, power line:-?, bond wire may all have problems. But now i want to know if 1~5V amplitude is too high. is it dangerous?
 

What does it mean 1~5V ?? Is it variable ?? Or Output level 4Vpp differential?
If it's so, 2Vp single ended output is normal...
 

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