Help for understanding an Op-amp circuit ...

[FvM]

I think, that's not correct. The circuit, of course, is NOT floating. The dc bias is provided (for both input terminals) through the feeedback network.

@LvW: Simple question to prove or disprove your assumption: Which voltage level will be set through the feedback network, and why? In case of doubt, I'm referring to IC1B in figure 1-1, post #1.
@KerimF: It would be useful for others, if you can post the zipped *.asc file of your LTSpice simulation.

 

[LvW]

Hi FvM, yes - you are right, of course. Unfortunately, I have concentrated myself on the last drawing provided by kerimF only.
That was my error, sorry.Referring to the original drawing the opamp outpout is in saturation.
LvW

 

[KerimF]

KerimF: And what is amazing in the circuit, is that IC1B is floating, it has no DC bias at all

I think, that's not correct. The circuit, of course, is NOT floating. The dc bias is provided (for both input terminals) through the feeedback network.

Please if you are referring to IC1B, its output (pin 7) is floating since there is no DC path to any of its two inputs (Pin 6 and pin 5). Let me agree with you and ask what is the DC voltage of pin 7 ?

KerimF, another comment: I am not sure if your simulation arrangement (and the corresponding results) are really helpful since you have suppressed R3=10 k (see the original drawing).

I guess you refer to R3 belonging to the next stage which is not considered yet in my analysis. The circuit around IC1B could be viewed as a load to IC1A opamp. But its loading effect is practically negligible if we remember that the internal resistance (impedance) of an opamp is relatively very small (a few ohms for example, if not less).

I don't expect you believe anything I say because the last word comes usually from what one gets personally from any 'real' experiment or what fits his developed set of knowledge based on his own logic. For instance, I never assumed any of my great teachers as being a prophet and I always doubt in anything I read/hear/see from others since they are all human beings as I am. :wink: But obviously, it is much easier for someone to live if he can let some others think and decide for him. :smile:

Kerim

Edited:
Sorry I didn't notice the page 2 of this thread when I wrote the reply.

 

[KerimF]

@KerimF: It would be useful for others, if you can post the zipped *.asc file of your LTSpice simulation.

You are right, but yesterday I couldn't upload other than images. Today things returned to normal here.

@No22Ben
In my post #19, I asked you if you heard of Thevenin Theroem. I like to point out that in this particular circuit (IC1A), we can find its voltage gain formula (Vout/Vin) rather directly even in the presence of the variable potentiometer VR1. And perhaps you can make it yourself; node Vn (Tap point) is always at zero volt and the input current of the opamp can be negleted.

 

[LvW]

Kerim, thanks for your response.

Please if you are referring to IC1B, its output (pin 7) is floating since there is no DC path to any of its two inputs (Pin 6 and pin 5). Let me agree with you and ask what is the DC voltage of pin 7 ?

I guess you refer to R3 belonging to the next stage which is not considered yet in my analysis. The circuit around IC1B could be viewed as a load to IC1A opamp. But its loading effect is practically negligible if we remember that the internal resistance (impedance) of an opamp is relatively very small (a few ohms for example, if not less).

I think, pin7 (original drawing) is not "floating", but in saturation (negative power rail) because there is a dc path to both inputs providing positive (nearly) 100% dc feedback. Thus, the voltage at pin7 is app. identical to the power rail.

Regarding R3 there was a misunderstanding. Sorry for that. By mistake, I assumed that your were evaluating the 2nd stage.
Of course. I don't expect much influence from opamp loading.
LvW

 

[KerimF]

Hi LvW,
I see your point. I meant by floating... not properly biased. And you are right, the output will likely be saturated (up or down) and if the two inputs are very well balanced then the external leakage currents will determine the idle state of the opamp... that is why I preferred to use the word floating that means undetermined. If we remove C3, the problem would be solved and all be happy... since pin 7 can rest on the ground at last :smile:

Edit:
May I add that wrong circuits are much more difficult to discuss than the good ones.

 

[thannara123]

refer it https://elearning.algonquincollege.com/coursemat/saurioc/ELE-2-CENG/ELE2-CE-NOTES/BASICOPA.pdf

 

[KerimF]

refer it https://elearning.algonquincollege.com/coursemat/saurioc/ELE-2-CENG/ELE2-CE-NOTES/BASICOPA.pdf

I agree with you. Most answers could be found on the internet.

I think these answers are more useful to the experts than new students. A professional (having experience in a field) can even read in between the lines when he reads what could be related to a project he is working on and he usually discovers some missed important notes, if not also some errors as well (minor or serious). On the other hand, a student will have no choice but to read a scientific reference as if it were a bible hence many questions come into his mind and here is the role of a teacher to answer his questions (mine were mostly silly ones when I was a student) step by step till the student is able to stand on his feet on a solid ground... and run away :wink:

In my case, every time I need a rather complex mathematical formula or electronic solution (hardware or software), I surely try to get it first from a source and I don't depend on my 'short' memory. And I may access the same formula (or one of my own old works) many times on the same day while working on a new design.

 

[LvW]

I agree with you. Most answers could be found on the internet.

Answers....yes, may be. But explanations?
For example, the link as given above (from Thannara) does not give any information about the validity and the exactness of the presented formulas (what means: opamp ideal? Which parameters are neglected/simplified)?
Or take the circuit under discussion:
*Where in the internet one can find something about combined positive/negative dc feedback?
*Where one can find some explanations about an inverting stage with a resistor (and its role) beween the inv. input and ground (see stage 1 in the example under discussion)?

In summary, I am afraid, via the internet you can collect some „mosaic pieces“ only – but you won`t get the whole and complete picture without a good book and/or a good teacher.

But - in general - I share your sight, Kerim.

Regards
LvW

 

[KerimF]

Hi LvW... and that is why I said ... 'Most' and not 'All' :smile:

 

[No22Ben]

ok guys, I had spent almost 1 day to do the nodal analysis with my coursemate...here's the link, 1st and 2nd Circuit Block Analysis.pdf ...
tell me if we had made any mistake , thanks alot...

 

[KerimF]

ok guys, I had spent almost 1 day to do the nodal analysis with my coursemate...here's the link, 1st and 2nd Circuit Block Analysis.pdf ...
tell me if we had made any mistake , thanks alot...

As usual you keep doing well. Nice work.
So what do you think will happen if n=0 (at VR1)? I mean what will the gain be?

 

[LvW]

ok guys, I had spent almost 1 day to do the nodal analysis with my coursemate...here's the link, 1st and 2nd Circuit Block Analysis.pdf ...
tell me if we had made any mistake , thanks alot...

Hi No22Ben,
I suppose, there is no mistake.
However, don't forget: Derivation of a formula is only the first of two steps. The second important step is: Interpretation of the result!
In this context, the following comments:
* In the first drawing the resistor R2 does not appear in the gain formula. Why not? Does it have no influence on circuit behaviour?
Answer: Yes, it has a big influence on stability properties (and on the bandwidth) , however, this can be verified only if the opamp is considered as a real and non-ideal device.
* As mentioned recently already by FvM, the 2nd stage acts as a 1st order allpass (see the last formula that is a typical allpass expression), however, the input node of this stage must provide a dc path (i.e. not ac coupled) due to opamp bias problems as discussed before.
* By the way: The numerator of the last formula (allpass transfer function) can be simplified because two terms cancel each other. This simplifies any interpretation.
Regards
LvW

 

[FvM]

The allpass transfer function can be further reduced. It should end up

Vout/Vin = -(1-sRC2)/((1+sRC2) for R1=R3.

Your intermediate result has a similar form, but one factor different. Thus I guess, there's a fault somewhere on the way.

 

[LvW]

I forgot to mention that the 2nd stage is a "typical" allpass for correct dimensioning of R,C values.

 

[No22Ben]

or can you try to help me derive ? becuz I had tried many times, and still cannot end up with Vout/Vin = -(1-sRC2)/((1+sRC2) >.<

 

[KerimF]

or can you try to help me derive ? becuz I had tried many times, and still cannot end up with Vout/Vin = -(1-sRC2)/((1+sRC2) >.<

After 1 ---> 2
On your 4th derived equality, the last term -sCR1 is added by mistake.
So in your result, the term -s(R3/R1 + 1) will become -sR3/R1 only.