[SOLVED] Help for Sine Wave inverter

[swapan]

Hi friends,

After having basic inputs from this forum regarding sine wave inverter employing H Bridge, I have come to the conception that high side MOSFETs are driven by pulse of 50Hz signal and low side MOSFETs are driven by PWM pulse of carrier frequency. Please rectify me if the conception is wrong.

To prevent shoot through current during transition period, dead-band delay is incorporated. Please let me know which signal is to be delayed, high frequency pulse or low frequency pulse?

During charging process, the induced voltage depends on duty cycle of applied signal. Please state the typical value of frequency of the signal applied to the boost converter.

Regards

swapan

 

[picgak]

You are right about the concepts
dead-band delay is incorporated for low frequency pulse
frequency depend on the inductance

 

[betwixt]

No!

All arms of the bridge are driven by pulses at PWM 'carrier' frequency. The dead band is a small delay between one arm turning off and the next turning on so the bridge transistors have time to fully turn on or off.
The 50Hz is used to modulate the on/off ratio of the PWM pulses, not the bridge itself.

Brian.

 

[Tahmid]

Hi friends,

After having basic inputs from this forum regarding sine wave inverter employing H Bridge, I have come to the conception that high side MOSFETs are driven by pulse of 50Hz signal and low side MOSFETs are driven by PWM pulse of carrier frequency. Please rectify me if the conception is wrong.

This is fine. 50Hz pulses are applied to the high side MOSFETs and high frequency pulses are applied to the low side MOSFETs.

To prevent shoot through current during transition period, dead-band delay is incorporated. Please let me know which signal is to be delayed, high frequency pulse or low frequency pulse?

During the dead-band period, all the MOSFETs are to be kept off.

During charging process, the induced voltage depends on duty cycle of applied signal. Please state the typical value of frequency of the signal applied to the boost converter.

This is up to you. In the 16F72-based inverters, a frequency between 3-8 kHz is usually used. If you instead use a frequency of 16kHz or higher, it's better, since audible noise is reduced or eliminated. And filtering is "easier" since the time period is smaller.

Hope this helps.
Tahmid.

 

[swapan]

Thanks picgak for your response. Really it will encourage me to go ahead.

swapan

- - - Updated - - -

Tahmid,

So kind of you. Now my doubts are very much clear. Thaaaaaanks.

swapan

 

[swapan]

Mr. Tahmid,

This is nothing but my sheer curiosity. During toggling gate drive, duty cycle of PWM is 0 -which means low side MOSFET is virtually in OFF position. Would it not prevent shoot through current danger without extra dead band delay?

regards

swapan

 

[Tahmid]

The deadband delay (may also be called deadtime) is used to prevent shoot through due to conduction of MOSFETs in the same leg.

First, let's say A and C are being driven - A at 50Hz, C at 16kHz.
Then, in the next half cycle, we must drive B and D.
A was driven at 50Hz. Which means that during the entire half cycle during which C was pulsed at 16kHz, A was on. Now, we will turn D on and pulse B. But whenever B is pulsed on, there will be a short circuit as A is on and current will flow through A through B and there will be a short. So, the dead-band delay is provided before D and B are to be driven. During this dead-band delay, A is turned off and kept off. C is also turned off. In this way, a short-circuit is prevented.

Hope this helps.
Tahmid.

 

[swapan]

Thanks Tahmid. Actually my curiosity is : Each diagonal pair of MOSFETs are toggled at 180°/360° of a cycle i.e. after every half cycle where duty cycle of 16KHz signal is 0% (as per sine table). If 0% duty cycle means total OFF position, then shoot-circuit will not complete through lower MOSFETs near toggling position. Though it may be a silly question, please comment.

regards

swapan

 

[Tahmid]

Sine table affects the lower MOSFET. So, at the end of the half-cycle when A was kept on, C became 0. But A is still on, and when the sine table values are used to drive B, there will be a short circuit through A and B. So, during the dead-band delay, A and C are both turned and kept off, so that during the next half-cycle, they're both off.

Hope this helps.
Tahmid.

 

[swapan]

Thanks Tahmid, it helped me a lot.


regards

swapan

 

[picgak]

Sine table affects the lower MOSFET. So, at the end of the half-cycle when A was kept on, C became 0. But A is still on, and when the sine table

Hope this helps.
Tahmid.

Tahmid cant we do without deadband delay if both side ends of sinetable have zero's

 

[Tahmid]

Thing is, deadband delay is the time during which the MOSFETs are kept off to prevent cross-conduction. Knowingly or unknowingly. there is always a gap otherwise the circuit will be shorted. And, what is the problem with using a longer gap if required? The ECCP module gives you the option to generate the delay. However in many cases, the delay may not be required. The change of bridge direction and the instruction time of the PIC may be sufficient toprevent cross-conduction. So keep this in mind when designing the driver. Ensure that the driver does not introduce any undesired or problematic delay.

Hope this helps.
Tahmid.