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help for frequency divider

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zhangpengyu

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Hi
How can I divide frequency by odd numbers(such as 3)?



zhpy
 

For division by 3 use 2 JK flip-flops or for other divisions go to frequency dividers site:
**broken link removed**
Regards,
IanP
 

u can design a modulo-3 counter if duty cycle don't require
 

if you want to get a %50 duty cycle clk,you must use your source clk's posedge and negtive edge!
 

dolby.yang is right. If 50 % duty is required
- extract pos and neg edge from input signal,
- OR them,
- give ORed output to counter with parallel loading diving by 3
- and then get the 50 percent duty by normal D trigger dividing by 2 .
 

please look up the book about the divider,this way is simple and better.
 

You Can achieve the frequency divider by any odd number, but u have a no 50% duty cycle, but still u can achieve a 50 % duty cycle but it is complex in hardware wise u have to concentrate on both positve as well as negative edge of the clock, so need positive and negative edge triggered flip flops.
Regards
Raghu
 

for example 3, following is sample code:

always @(posedge clk or negedge rst_n)
begin
if (rst_n)
counter <= #1 2'h0;
else if (counter == 2'h2)
counter <= #1 2'h0;
else
counter <= #1 counter + 2'h1;
end

assign clk_divided_by_3 = counter[1];





zhangpengyu said:
Hi
How can I divide frequency by odd numbers(such as 3)?



zhpy
 

If duty cycle is require, both posedge and negedge will be used to generate you 3 frequency divider.
 

For divider by odd:
you can use a PLL for obtaining any freq.
Bests.
 

hi
i feel it is possible using a 3 bit ring counter....does ne1 agree???
 

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