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help Error for LPM Ram synplify.

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cltong

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The error is:
@E: CG165 :"E:\verilog\new\cqpic100d\PIC100D\VERILOG\DATARAM.V":27:10:27:22|Illegal defparam. parameter LPM_WIDTHAD cannot be found in module lpm_ram_dq.

the source code of verilog:

module dataram(addr, read, write, clk, datain, dataout);
input [8:0] addr;
input read;
input write;
input clk;
input [7:0] datain;
output [7:0] dataout;

lpm_ram_dq u (
.data(datain),
// .address(addr), // Full implementation of BANK3-0
.address(addr[6:0]), // BANK0 only
// .inclock(clk),
.outclock(clk),
.we(write),
.q(dataout)
);

// defparam u.LPM_WIDTHAD = 9; // LPM_WIDTHAD (Full implementation of BANK3-0)
defparam u.LPM_WIDTHAD = 7; // LPM_WIDTHAD (BANK0 only)
defparam u.LPM_WIDTH = 8;
defparam u.LPM_INDATA = "UNREGISTERED";
defparam u.LPM_ADDRESS_CONTROL = "UNREGISTERED";
defparam u.LPM_OUTDATA = "REGISTERED";

endmodule
 

jcchan

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You can try another method, for example you can delcare " reg [7:0] mem [0:127]", synplify will automatic to synthesis to be fpga ram macro by device.
 

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