you can use the conventional phase frequency detector consisting of 2 flipflops and an and gate. you can find the information on it in most of the books. when you design digital gates, let's say an inverter, make the pmos 3 almost 3 times larger than the nmos so that you'll have same delays for 0>1 and 1>0 transitions and a threshold voltage of VDD/2. consider charge sharing so size the transistors at a network (nmos or pmos network) accordingly. if you have dynamic nodes in your flipflop, consider regeneration structures which consist of a single transistor. you can use TSPC logic for flipflops if you need high speed phase detector. you can also use your flipflops for the counter