Help~~cadence problems~!!

[zhangjavier]

What does the following notices mean when using Analog design envoriment to simulate a circuit??

"
Only one conntection to the folowoing nodes....

No dc path from node...to ground.

"

These notices appeared when I simulated the circuit after parasictic extractred. In fact there were no such notices when I just simulated the schematic. The shematic and the layout mathed.

I don't why. How could the parasitic elements change the circuit so much that even block the dc path??

And I also want to know how to find some node or parasitic element in the layout by knowing its name??

Thank you so much~!!

 

[tsinghua]

It is fine. When you do post-layout simulation with parasitics, there should be many nodes without DC paths such as dangling paths.

 

[zhangjavier]

It is fine. When you do post-layout simulation with parasitics, there should be many nodes without DC paths such as dangling paths.

Hey, you are from tsinghua??so what's your ID on SMTH??

 

[saberbf]

1st: to solve the problem you can set initial condition for that node or create a dc path for it
2nd:use SHORT toolbar

 

[visualart]

you shall check & save your schematci , and simulate using the new netlist.

 

[test_out]

I aslo met this message and still dont know how to solve.
Hi saberbf, can you tell me how to set set initial condition for the error node?

Thanks