Help: ATPG simulation error

[handsome]

In my soc, there are some clock sync DFF. For example, in usb module, there are some DFFs use clk_48 as clock and clk_12 as data, that means in normal function mode DFFs will use clock of clk_12 as data. But in scan mode, clk_12 and clk_48 will be one clock, that is test_clk, then in scan capture, these DFFs will capture violation. At first, I think this is the reason what lead to my atpg simulation fail. So when insert scan, I set_scan_element false these DFFs. But my atpg siulation fail too. I use ncverilog simulator, and use two parameter nospecify and zero_delay_mode.

How can i deal with this problem? Now I want to tmax do not care these DFF, is this doable? If yes ,How can do?

Thx.

 

[feel_on_on]

Maybe your spf never generated correctly .and u ough to introduce ur problem in detail.That's not relate to ncverilog ,i think

 

[stormwolf]

You circuit has multiply clock, so capture clock speed can't work well for all. We will reduce capture clock speed to fit all circuit. You can try to reduce clock speed . Above is for stuck-at.
You pattern has error for stuck-at or at-speed?

 

[dft_guy]

Any time you have clock used as data, you will have problems. It's a race condition, pure and simple. ATPG will not be able to predict the outcome, as it has no knowledge of timing.

The way I see it, you can do a one of a couple of different things... 1) gate off the data input to the FF during scan mode, or substitute another signal for the clock that is used as data for best fault coverage, or 2) take it out of the scan chain, and realize you will not be able to control or observe that FF during scan, and lose the fault coverage.

John
DFT Digest

 

[handsome]

ATPG simulaiton failure is because I have not back annoted sdf file.

With sdf back annoted, atpg simulation will pass except only two cell's error in one chain in a little few pattern . Why this ? I want to mask these two cells when run ATE test. My test coverage is 98%.

Another question, How to simulate netlist wrote by DC without sdf file?

About the clock sync DFF, I will modify my rtl code, add a mux before D port. When is scan mode, DFF will not use clock as its D input.

I am a newer.Thanks for you all.