module prefix_sum(
input [3:0] data_in,
input clk, rst, ld,
output reg [3:0] sum [0:3]
);
reg [3:0] temp = 4'b0000;
reg [1:0] num = 2'b0;
always @ (posedge clk) begin
if (rst) begin
sum[0] <= 4'b0000;
sum[1] <= 4'b0000;
sum[2] <= 4'b0000;
sum[3] <= 4'b0000;
end else if (!ld) begin
num <= 2'b0;
end else begin
temp <= temp + data_in;
sum[num] <= temp;
num <= num + 1;
end
end
endmodule
Are you are trying to store incoming data into a 4x4 array in the order they are received as per the state of "ld"?when i checked syntax, i just have warning that : Port sum must not be declared to be an array
but whenever want write testbench and check behavioral syntax the code dont work at all.
Yes, the compiler will not allow you to represent dec(4) using a 2 bits!also for num <= num +1 have this warning : Result of 3-bit expression is truncated to fit in 2-bit target
These two you can deal with later. First get your simulation working.PAD symbol "clk" is not constrained (LOC) to a specific
location.
and
PAD symbol "clk" has an undefined IOSTANDARD.
I have no idea what it is.
Yes, I want to store results in 4 number with 4 bits in Sum[num].Are you are trying to store incoming data into a 4x4 array in the order they are received as per the state of "ld"?
It would also be nice to indicate your intention of your RTL code.
Yes, the compiler will not allow you to represent dec(4) using a 2 bits!
These two you can deal with later. First get your simulation working.
btw - If you have *just warnings* it would still be possible to proceed to simulation (although you are not likely to see the desired results). Is your TB driving all the necessary i/p signals?
You need to increase the reg size of your sum in that case. As I understand from #1, your num size should be equal to your array depth which has 4 bits, i.e depth=16.
So in your RTL if have to add to your code before incr num, something like,
if (num< 4'b1111)
increment num;
else
reset num;
When you are writing RTL you should think in parallel what h/w shall your code generate, rather than just obtaining the target functionality. Then you'll minimize such compiler warning messages.
check the logic for num, it is not being reset. don't initialise regs like that, it's a bad practice.
Standard Verilog doesn't support passing arrays through module ports. You will have to set your simulator and synthesis tools to use System Verilog. As of 2015.2 Xilinx simulator still does not accept arrays in module ports regardless of the SV switch (don't know if it is supported in 2016.2).when i checked syntax, i just have warning that : Port sum must not be declared to be an array
but whenever want write testbench and check behavioral syntax the code dont work at all. and give me this warning :
Port sum must not be declared to be an array
These are calling for constraints on the ports in your xdc file. If you don't have constraints on all your pins you will see these types of warnings. But why are you running anything else besides simulation, you should not be trying to implement the design at this time.Adnan86 said:PAD symbol "clk" is not constrained (LOC) to a specific
location.
and
PAD symbol "clk" has an undefined IOSTANDARD.
I have no idea what it is so i cant see simulation to know how it works.
maximum value of reg [1:0] num; is 2'b11, if you add 1 to this you end up with 3'b100, which according to Verilog assignment rules gets truncated to 2'b00.Adnan86 said:also for num <= num +1 have this warning : Result of 3-bit expression is truncated to fit in 2-bit target
data_in => 1, 3, 2, and 5
sum[0] = 1
sum[1] = 4 (1+3)
sum[2] = 6 (1+3+2)
sum[3] = 11 (1+3+2+6)
Still, it is bad practice, as evidenced by OP's way of 'describing hardware'. Just add a reset.
end else if (!ld) begin
num <= 2'b0;
I'm also having a difficult time determining what you are trying to accomplish, your first post and subsequent explanations don't clear this up.
Are you trying to set the sum[0], sum[1], sum[2], & sum[3] values with intermediate summations of data_in.
e.g.
or are you trying to do something entirely different than that?Code:data_in => 1, 3, 2, and 5 sum[0] = 1 sum[1] = 4 (1+3) sum[2] = 6 (1+3+2) sum[3] = 11 (1+3+2+6)
yes , as you said my point is :
Code:data_in => 1, 3, 2, and 5 sum[0] = 1 sum[1] = 4 (1+3) sum[2] = 6 (1+3+2) sum[3] = 11 (1+3+2+6)
- - - Updated - - -
Well in the case of num
it can be set to 0 when ld == 0, though this seems kind of backwards as I would assume ld stands for LOAD. Which seems to mean that when you are loading you do the storing...hmm, maybe that is the intention to initialize the array with intermediate summations? If this is the case the temp should have been added to this same section of code so that it is initialized to 0 before adding four data_in values together.Code:end else if (!ld) begin num <= 2'b0;
data_in => 1, 3, 2, and 5
sum[0] = 1
sum[1] = 4 (1+3)
sum[2] = 6 (1+3+2)
sum[3] = 11 (1+3+2+6)
yes my point is :
Code:data_in => 1, 3, 2, and 5 sum[0] = 1 sum[1] = 4 (1+3) sum[2] = 6 (1+3+2) sum[3] = 11 (1+3+2+6)
I just guessed that this was what you were trying to do.
Let this be a lesson to you and others, give an example of what you expect your code to do, instead of a rambling explanation that doesn't translate well and a functionality that can't be determined from "broken" code.
I still don't quite know what it is that you think is wrong with the simulation or if it is even a simulation problem you are having...no testbench and implementation warnings...probably means you are not running simulation on the design?
module prefix_sum(
input [3:0] data_in,
input clk, rst, ld,
output reg [3:0] sum [0:3]
);
reg [3:0] temp ;
reg [1:0] num ;
always @ (posedge clk) begin
if (rst) begin
sum[0] <= 4'b0000;
sum[1] <= 4'b0000;
sum[2] <= 4'b0000;
sum[3] <= 4'b0000;
temp <= 4'b0000;
num <= 2'b00;
end else if (!ld) begin
num <= 2'b00;
end else if (num <= 2'b11) begin
temp <= temp + data_in;
sum[num] <= temp;
num <= num + 1;
end
end
endmodule
module test_sum;
// Inputs
reg [3:0] data_in;
reg clk;
reg rst;
reg ld;
// Instantiate the Unit Under Test (UUT)
prefix_sum uut (
.data_in(data_in),
.clk(clk),
.rst(rst),
.ld(ld)
);
initial repeat (10) clk = ~clk;
initial begin
// Initialize Inputs
data_in = 0;
clk = 0;
rst = 1;
ld = 0;
#15 ld = 1; rst = 0; data_in = 4'b0010;
#10 data_in = 4'b0011;
#10 data_in = 4'b0001;
#10 data_in = 4'b0100;
//#20 $stop;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
Code Verilog - [expand] 1 output reg [4*4-1:0] sum,
Code Verilog - [expand] 1 sum[4*num +:4] // the 4*num groups by 4 bits and +:4 means that the LSB is 4*num and the number of bits is 4 so 3:0
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?