help about Verilog model of a pipelined maximizer/minimizer

Similar threads

• K

  explanation of how to translate C code into verilog

  • Started by keikaku
  • Mar 5, 2024
  • Replies: 10

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  [SOLVED] Please help for Data transferring between Verilog Modules

  • Started by EDA_hg81
  • Aug 12, 2023
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  The reason of Verilog signed math calculation error

  • Started by EDA_hg81
  • Sep 17, 2023
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  How can I run verilog code with data at a specific time in the past?

  • Started by alexis57
  • Jan 28, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  How do I assign decimal values in verilog?

  • Started by mahesh_namboodiri
  • Jan 31, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design