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help! about IP core simulation model

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Matrix_YL

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Hi all
In new version of ISE,some ip cores(ISE 8.1's IP core especially)have no verilog behavioral model.when IP Core generated will have following indication:
“The chosen IP does not support a Verilog behavioral model, generating a Verilog structural model instead.”.
What's difference between Verilog behavioral model and a Verilog structural model?
How can I do behavioral simulations for these IP Cores ?

thx in advance
 

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