help! about IP core simulation model

[Matrix_YL]

Hi all
In new version of ISE,some ip cores(ISE 8.1's IP core especially)have no verilog behavioral model.when IP Core generated will have following indication:

“The chosen IP does not support a Verilog behavioral model, generating a Verilog structural model instead.”.

What's difference between Verilog behavioral model and a Verilog structural model?
How can I do behavioral simulations for these IP Cores ?

thx in advance