help a noob - VHDL code

[jamesegg]

Hi guy, I'm getting stuck in a rut here. I'm very new to VHDL so please be paitent

How can I alter mid to allow for varied bit lengths? If I alter the value from (3 downto 0) it throws up errors of unexpected bit lengths! Any explanation would be much apreciated, thanks in Advance.

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Code VHDL - [expand]
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Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
 
Entity ALU is
    Port ( A, B : in  STD_LOGIC_vector (3 downto 0);
           Sel : in  STD_LOGIC_vector (3 downto 0);
              Z: out STD_LOGIC_vector (3 downto 0));
              
              
                          
End ALU;
Architecture job of ALU is
signal Mid: STD_LOGIC_vector (3 downto 0);
 
 
Begin
Process (sel,A,B)
Begin 
        if (sel="000") then Mid <= A or B; 
        elsif (sel="001") then Mid <= A and B;
        elsif (sel="010") then Mid <= A nor B;
        elsif (sel="011") then Mid <= A nand B;
        elsif (sel="100") then Mid <= A xor B;
        elsif (sel="101") then Mid <= A nand B;
        elsif (sel="110") then Mid <= A xnor B;
        else Mid <= std_logic_vector(unsigned(A) + unsigned(B));        
        end if;
End process;
 
Process (sel,mid)
Begin
        if (sel="111") and (mid <"00101") then Z    <= "1000" ;
        elsif (sel="111") and (mid <"01001") then Z <= "0100" ;
        elsif (sel="111") and (mid <"01101") then Z <= "0010" ;
        elsif (sel="111") and (mid <"10001") then Z <= "0001" ;
        else Z <="0000";
        end if;
End process;  
End  job;

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[TrickyDicky]

use a generic:

Entity ALU is
generic (
  WIDTH : positive
)
port (
  a : std_logic_vector(WIDTH-1 downto 0);

--etc

 

[FvM]

It's not clear what you mean with "varied bit length" and why it should be used in the VHDL example.

The addition

std_logic_vector(unsigned(A) + unsigned(B));

has a 4-bit result width according to VHDL rules.

There won't be a problem however to generate a carry in the addition and get a 5 bits wide result. One summand has to be extended to 5-bit to do so, e.g. by a '0' & concatanation.

The purpose of the code can't be well determined because the result mid is presently discarded for sel /= "111".

 

[jamesegg]

TrickyDicky - Would that not just alter the length of the input port bits?

FvM - I confused as the signal sel is declared as a 4 bit vector which is derived from A, B. If these are added together you are saying I will still only get a 4-bit result currently? In which case using a syntax something along the lines of :

else Mid <= std_logic_vector(unsigned("0" & A) + unsigned("0" & B));

The purpose is for an assignment so it's more of an exercise than functionality.

Thanks for the help

 

[TrickyDicky]

TrickyDicky - Would that not just alter the length of the input port bits?

yes, but you can have variable length arrays internally using that generic too.