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ad2 area delay
Hello everyone,
I hope everyone are fine. I am an EE student and have been asked to Design a 32-bit Static CMOS Adder with Minimum Area Delay-Squared Product. Well I am looking for some ideas and help on getting me started. Any kind help would do a lot to me.
SOME NOTES GIVEN TO ME.
The goal is to design an unsigned 32-bit adder using static CMOS cells, which has the minimum AD2 figure of merit (Area.Delay2 product.) Your adder architecture can be any of the logarithmic (tree) adder, for example, the Brent-Kung or the Ladner-Fischer adder. You may alternatively implement a variable-length carry-bypass adder or variablelength carry-increment adder. The choice is yours. Bonus credit goes to those designs achieve the minimum AD2 value. Use of dynamic logic circuits or any kind of pipelining is strictly forbidden.
The inputs of the adder are the input carry (C0) and the operands A (A1 to A32) and B (B1 to B32).The outputs of the adder are the sum output bits (S1 to S32) and the outgoing carry (C32). Assume that the sum and final carry outputs have a fanout of 4 load, i.e., each is driving a capacitive load of 4Cinv, where Cinv is the gate capacitance of the minimum-size static inverter where (W/L)p=2*(W/L)n.
Suggested Design Steps
(a) Examine the various adder architectures and pick one that you think will have the best overall performance in terms of the AD2 figure of merit.
Hint: You may want to implement the gray box and black box logic elements and
buffers (see lecture notes on adders for definition of these boxes), extract and
characterize each for speed and area, and use the information to estimate the AD2
value for the whole design. This will then allow you to pick the best target
architecture early on without having to go thru time-consuming architecture change
after full layout.
(b) Instantiate and floorplan the various gray and black boxes as per corresponding PG network architecture as compactly as you can. Make sure to include cells that calculate the bitwise propagate and generate signals and the cells that calculate the sum bits and the final carry out bit (C32).
(c) Connect the various cells while trying to minimize the wire lengths on your timing critical paths and minimize area of the rectangle that encloses your overall design layout (all of your cells and the routing including power and ground rails.) The area of this minimum enclosing rectangle will set the Area value in the AD2 metric. You may size transistors, insert buffers, do rerouting, input re-ordering, etc. in order to minimize the worst-case propagation delay from carry in to the output bit that is being set (the delay is most likely from C0 to S32.) This is all done in MAGIC.
(d) Extract the layout to IRSIM and check the functionality of your adder using the test bench. We will provide you with a large set of typical input patters.)
(e) Extract the layout to HSPICE and check the performance of your adder for a few worst-case input patterns and report the largest of all these delays. This last value will set the Delay in the AD2 metric. We will provide you with a small set of worst-case patterns. Assume that both inputs and carry in come at the same time and have a rise time of 10 ps.
(f) Calculate the AD2 metric for your design.
I can design an 32-bit adder but I am confused as to how to Minimum Area Delay-Squared Product and i mean which factors to consider and how to reduce is bit of problem to me. Any small ideas or help will help me a lot.
Thanking you all for your time and patience
wishes
MK
Hello everyone,
I hope everyone are fine. I am an EE student and have been asked to Design a 32-bit Static CMOS Adder with Minimum Area Delay-Squared Product. Well I am looking for some ideas and help on getting me started. Any kind help would do a lot to me.
SOME NOTES GIVEN TO ME.
The goal is to design an unsigned 32-bit adder using static CMOS cells, which has the minimum AD2 figure of merit (Area.Delay2 product.) Your adder architecture can be any of the logarithmic (tree) adder, for example, the Brent-Kung or the Ladner-Fischer adder. You may alternatively implement a variable-length carry-bypass adder or variablelength carry-increment adder. The choice is yours. Bonus credit goes to those designs achieve the minimum AD2 value. Use of dynamic logic circuits or any kind of pipelining is strictly forbidden.
The inputs of the adder are the input carry (C0) and the operands A (A1 to A32) and B (B1 to B32).The outputs of the adder are the sum output bits (S1 to S32) and the outgoing carry (C32). Assume that the sum and final carry outputs have a fanout of 4 load, i.e., each is driving a capacitive load of 4Cinv, where Cinv is the gate capacitance of the minimum-size static inverter where (W/L)p=2*(W/L)n.
Suggested Design Steps
(a) Examine the various adder architectures and pick one that you think will have the best overall performance in terms of the AD2 figure of merit.
Hint: You may want to implement the gray box and black box logic elements and
buffers (see lecture notes on adders for definition of these boxes), extract and
characterize each for speed and area, and use the information to estimate the AD2
value for the whole design. This will then allow you to pick the best target
architecture early on without having to go thru time-consuming architecture change
after full layout.
(b) Instantiate and floorplan the various gray and black boxes as per corresponding PG network architecture as compactly as you can. Make sure to include cells that calculate the bitwise propagate and generate signals and the cells that calculate the sum bits and the final carry out bit (C32).
(c) Connect the various cells while trying to minimize the wire lengths on your timing critical paths and minimize area of the rectangle that encloses your overall design layout (all of your cells and the routing including power and ground rails.) The area of this minimum enclosing rectangle will set the Area value in the AD2 metric. You may size transistors, insert buffers, do rerouting, input re-ordering, etc. in order to minimize the worst-case propagation delay from carry in to the output bit that is being set (the delay is most likely from C0 to S32.) This is all done in MAGIC.
(d) Extract the layout to IRSIM and check the functionality of your adder using the test bench. We will provide you with a large set of typical input patters.)
(e) Extract the layout to HSPICE and check the performance of your adder for a few worst-case input patterns and report the largest of all these delays. This last value will set the Delay in the AD2 metric. We will provide you with a small set of worst-case patterns. Assume that both inputs and carry in come at the same time and have a rise time of 10 ps.
(f) Calculate the AD2 metric for your design.
I can design an 32-bit adder but I am confused as to how to Minimum Area Delay-Squared Product and i mean which factors to consider and how to reduce is bit of problem to me. Any small ideas or help will help me a lot.
Thanking you all for your time and patience
wishes
MK