Goover
Newbie level 1
due to stuck clock or clock enable
Hello,
I'm trying to implement a design with the Quartus 2 (v6) software for my Cyclone II FPGA.
I needed 80 counters for my design, 1 created a block of 4 counters, placed 10 of them in a design file and created a symbol file. This all synthesises, and the logical simulations are fine too.
But when I placed the 80counter block in my overall design file it first worked fine. But since a day or so I get aprox. 1400 warnings all about the same.
As you can see the warning occurs in a standard lmp_counter.. it seems like the clk signal is not connected in the correct way. But I can't find any abnormalities.
I named a pin as 'CLK' and specified the timing settings (50mhz)..
Help anyone?
Hello,
I'm trying to implement a design with the Quartus 2 (v6) software for my Cyclone II FPGA.
I needed 80 counters for my design, 1 created a block of 4 counters, placed 10 of them in a design file and created a symbol file. This all synthesises, and the logical simulations are fine too.
But when I placed the 80counter block in my overall design file it first worked fine. But since a day or so I get aprox. 1400 warnings all about the same.
Code:
Warning: No clock transition on "80Counters:inst|Total43:inst8|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_gdj:auto_generated|safe_q[0]" register due to stuck clock or clock enableAs you can see the warning occurs in a standard lmp_counter.. it seems like the clk signal is not connected in the correct way. But I can't find any abnormalities.
I named a pin as 'CLK' and specified the timing settings (50mhz)..
Help anyone?