So yes, barry points out the code you posted is clearly not describing any hardware - it looks as though you're trying to write software in VHDL - VHDL is a hardware description language. If you could use integers for inout (which you cannot - and Ill explain why in a minute) then it would always be assigned the last value that triggers in the loop, which would be the previous value of b from the last time the process triggered plus the highest value of i for which a(i) = '1' is true. (This is going to create latches, and you really dont want latches). Also, like barry says, B should really be a buffer, not inout, because it doesnt read a value external to the entity.
The reason inouts cannot be integers, is because integer is not a resolved type (ie. signal can be driven from mutliple sources). The only resolved type in standard VHDL is the std_logic type (and therefore arrays of std_logic - std_logic_vector, unsigned and signed). So inouts HAVE to be one of these types, because you could, in theory, drive it from inside and outside the entity.
Inouts are meant for tri-state buffers, not reading an out internally. I get the feeling you probably dont know what a tri-state buffer is - I suggest you read about one.
Overall - it looks like you're a software guy. If thats the case - I suggest you forget about HDL for now and go read a book about digital logic and get to understanding how that works. When you understand it, draw the circuit (on paper, visio etc) that solves the problem you are trying to solve. Only then can you write HDL.
HDL stands for Hardware description language, so if you dont know what circuit you're trying to create, how do you expect to describe it?