Hello, VHDL code for vector to integer conversion needs some light to be shed upon

[RAVINDRA SINGH]

hello everyone, i have a question that popped up during the design of vector to integer code. Leaving asides the use of variables inside the process statement , if we use an inout signal and update it as in the following code, i thought it would work, however it's giving unexpected results. although i have a theory for that, i don't know if it's correct or not, so please shed some light on the unexpected results.

code:

---

Code VHDL - [expand]
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entity inout_sig is
    Port ( a : in bit_vector(7 downto 0);
           b : inout integer:= 0);
end inout_sig;
 
architecture arch_iosig of inout_sig is
 
begin
    process(a)
       variable x :integer;
    begin
     
     for i in 0 to 7 loop
        
         if a(i)='1' then x:=1;
         else x:=0;
        end if;
 
        b<= b + x*(2**i);
     end loop;
     end process;
    
end arch_iosig;

---

My thought of it:
well, i tried various methods and found that whenever there are multiple statements for driving a signal in the sequential manner, then the latest signal driver only drives the signal and hence the value assigned to the signal depends on the last signal driver. So, here ,in this example, due to the loop , multiple driver statements for the signal b are being created and its value is updated only by the last signal driving statement. Use of the inputs : "00000011" , "00000001" , "10000001" , "11000001" , "01000000" gives the results -0 , 0 , 128 , 256, 256 respectively. Please, shed some light on this, if i am going correctly about it.:idea:

 

[barry]

I wouldn't use inout for your "b" port. Use buffer or simply out. You are not reading from that port.

I think what you really want is to create a signal, b_s, and change your statement to

b_s<=b_s + x*(2**i);
b<=b_s;

Forget all the previous, I missed that loop statement.

Now that I look at it again, I have to ask: What are you actually trying to do?

Are you trying to read a value from port b, process it and then write it back to b eight times? That won't work.

 

[RAVINDRA SINGH]

I wouldn't use inout for your "b" port. Use buffer or simply out. You are not reading from that port.

I think what you really want is to create a signal, b_s, and change your statement to

b_s<=b_s + x*(2**i);
b<=b_s;

Forget all the previous, I missed that loop statement.

Now that I look at it again, I have to ask: What are you actually trying to do?

Are you trying to read a value from port b, process it and then write it back to b eight times? That won't work.

yes Barry, first of all , sorry for replying so late.
yes i am trying to read from port b , update it and again write to it y taking b as an in-out port, well what i saw that only the last statement is executed i.e to say the loop creates all the iterations but only processes the last iteration.
And may i ask u that why wud u say that it won't work?

 

[barry]

I think you need to totally rethink what you are trying to do and how to do it. I'm afraid there are many misconceptions evident in your code. The main problem is you've got a concurrent process which means everything happens 'instantly'. Also, a signal assignment only occurs at the end of the process, not multiple times within a process. For example:

process(a)
begin
     b<=x"1';
     b<=x"2";
     b<=x"3";
end process;

b will equal 3, it will NEVER have values of 1 or 2.

 

[TrickyDicky]

So yes, barry points out the code you posted is clearly not describing any hardware - it looks as though you're trying to write software in VHDL - VHDL is a hardware description language. If you could use integers for inout (which you cannot - and Ill explain why in a minute) then it would always be assigned the last value that triggers in the loop, which would be the previous value of b from the last time the process triggered plus the highest value of i for which a(i) = '1' is true. (This is going to create latches, and you really dont want latches). Also, like barry says, B should really be a buffer, not inout, because it doesnt read a value external to the entity.

The reason inouts cannot be integers, is because integer is not a resolved type (ie. signal can be driven from mutliple sources). The only resolved type in standard VHDL is the std_logic type (and therefore arrays of std_logic - std_logic_vector, unsigned and signed). So inouts HAVE to be one of these types, because you could, in theory, drive it from inside and outside the entity.

Inouts are meant for tri-state buffers, not reading an out internally. I get the feeling you probably dont know what a tri-state buffer is - I suggest you read about one.

Overall - it looks like you're a software guy. If thats the case - I suggest you forget about HDL for now and go read a book about digital logic and get to understanding how that works. When you understand it, draw the circuit (on paper, visio etc) that solves the problem you are trying to solve. Only then can you write HDL.

HDL stands for Hardware description language, so if you dont know what circuit you're trying to create, how do you expect to describe it?

 

[RAVINDRA SINGH]

Trickydicky....thank u for ur suggestion.I must admit that I have written the codes in form of a language rather than an HDL code for hardware. This is because I haven't been taught VHDL in terms of hardware, that's what I am pissed about till date, i want to know about the HDL in terms of hardware and am trying to do so,and I don't know how to go through it.Well for digital logic thing, I have read it a number of times and am OK at it, the only thing lacking is how HDL is related closely to the hardware and i need to know it badly. Inout concept has never been made clear to me by anyone i have asked and I am pretty bad at that.
Can u provide me an small example as how to use inout (equivalently to tri-state buffers whose input to output connection is controlled by a control signal)

- - - Updated - - -

I think you need to totally rethink what you are trying to do and how to do it. I'm afraid there are many misconceptions evident in your code. The main problem is you've got a concurrent process which means everything happens 'instantly'. Also, a signal assignment only occurs at the end of the process, not multiple times within a process. For example:

process(a)
begin
     b<=x"1';
     b<=x"2";
     b<=x"3";
end process;

b will equal 3, it will NEVER have values of 1 or 2.

Barry, can u please explain the concept of inout and buffers of VHDL in terms hardware and how to make synthesizable codes for them.
u told to do:

b_s<=b_s + x*(2**i);
b<=b_s;

i have encountered this thing while deriving a low frequency clock from a high frequency clock and did the same thing to avoid the clock skew.....how does it help.can u please shed some light on it in terms of hardware, i'll be very grateful.

 

[TrickyDicky]

inout should only be used for tri-state buffers. and you write a tristate in VHDL like this:

inout_port <= (others => 'Z') when OE = '0' else some_other_data;

You should only use inout when you are connecting to an external device that has a bi-directional connection. FPGAs have no internal tristates so these only get converted to muxes. Always use separate in and out ports wherever possible.

 

[RAVINDRA SINGH]

Thank u tickydicky, that was realy helpful. so FPGA's use mux for tri-state logic?

inout should only be used for tri-state buffers. and you write a tristate in VHDL like this:

inout_port <= (others => 'Z') when OE = '0' else some_other_data;

You should only use inout when you are connecting to an external device that has a bi-directional connection. FPGAs have no internal tristates so these only get converted to muxes. Always use separate in and out ports wherever possible.