what does this statement mean? what do you mean connected all input output to clock? how is this related to using timing constraints?
What are your timing constraints? Why didn't you provide them in the first post, so nobody has to ask you for them?
Again what timing constraints? Failing timing constraints isn't an error unless routing can't finish at all.
you don't do anything with those files as I recall they are just some intermediate output files. You want to look at the report files. FYI quartus documentation has what file extensions used and tells you what they are for. I don't use Intel parts so I haven't read the docs for years, but I do remember seeing those files, but never needed to look at them.
Gate level simulation is NOT how you change timing it only tells you how the design netlist behaves with the current place and route results. Random internet searches are not the way to learn. You should go on Intel's site and read their tutorials it is much better than some random google result.