[SOLVED] HDLCompiler:1316 Xilinx ISE 14.7

[snberg]

Hi!

I'm using the float_pkg of Bishop, and have come to the point where I want to do post-synthesis simulation. The synthesis and pre-synthesis simulations both work fine. When I try to run the post simulations, I get the following error messages:

ERROR:HDLCompiler:1316 - "E:/ISEprojects/float_ext_pack/netgen/map/float_point_package_module_map.vhd" Line 45: Index value <-23> is out of range [0:2147483647] of array <std_logic_vector>
ERROR:HDLCompiler:1316 - "E:/ISEprojects/float_ext_pack/netgen/map/float_point_package_module_map.vhd" Line 46: Index value <-23> is out of range [0:2147483647] of array <std_logic_vector>
ERROR:HDLCompiler:1316 - "E:/ISEprojects/float_ext_pack/netgen/map/float_point_package_module_map.vhd" Line 47: Index value <-23> is out of range [0:2147483647] of array <std_logic_vector>
ERROR:HDLCompiler:377 - "E:/ISEprojects/float_ext_pack/tb_float.vhd" Line 57: Entity port curr_xv does not match with type float of component port
ERROR:HDLCompiler:377 - "E:/ISEprojects/float_ext_pack/tb_float.vhd" Line 58: Entity port xv does not match with type float of component port
ERROR:HDLCompiler:377 - "E:/ISEprojects/float_ext_pack/tb_float.vhd" Line 59: Entity port d1 does not match with type float of component port

Is there a way to work around this? Or do I have to conclude that using this package does not work?

I'm targeting Virtex6 and using the synthesizable float package.

Thanks!

 

[ads-ee]

Well the 1316 error appears that you aren't using an unsigned type for indexing into the array.

The 337 errors seem self explanatory. Did you compare the component definition in tb_float.vhd and the actual component entity?

Regards

 

[snberg]

Yes, the component definition in tb_float.vhd and component entity are the same in the pre-synthesis code, but not the post-synthesis as the declarations are changed from "float" to "std_logic_vector" by the synthesiser.

I don't fully understand what you mean by using unsigned type for indexing?

The lines for the 1316 error are as follows:

curr_xV : in STD_LOGIC_VECTOR ( 8 downto -23 );
xV : in STD_LOGIC_VECTOR ( 8 downto -23 );
d1 : out STD_LOGIC_VECTOR ( 8 downto -23 ) ;

 

[ads-ee]

well you didn't post any of the code so how would I know the indices were 8 downto -23.

But you'll notice the error says out of range of 0:214748647 which just happens to be (2^31)-1, so it thinks the range is the natural numbers, which to me means you're indexing into the array and not the slv.

You should post the code and not just the error.

 

[TrickyDicky]

Only the fixed or float types can have -ve indices. Std_logic_vector cannot.

 

[snberg]

I know. The non-synthesised code is:

curr_xV : in float( 8 downto -23 );
xV : in float( 8 downto -23 );
d1 : out float( 8 downto -23 ) ;

Which synthesises to a code with:

curr_xV : in STD_LOGIC_VECTOR ( 8 downto -23 );
xV : in STD_LOGIC_VECTOR ( 8 downto -23 );
d1 : out STD_LOGIC_VECTOR ( 8 downto -23 ) ;

So, the synthesiser is changing it, not me. This is the code post-synthesis, post-map:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity float_point_package_module is
port (
clk : in STD_LOGIC := 'X';
enable : in STD_LOGIC := 'X';
curr_xV : in STD_LOGIC_VECTOR ( 8 downto -23 );
xV : in STD_LOGIC_VECTOR ( 8 downto -23 );
d1 : out STD_LOGIC_VECTOR ( 8 downto -23 )
);
end float_point_package_module;

architecture Structure of float_point_package_module is
signal STARTUP_V6_PWRUP_GTXE1_ML_INSERTED_ML_CFGMCLK_SIG : STD_LOGIC;
signal STARTUP_V6_PWRUP_GTXE1_ML_INSERTED_EOS : STD_LOGIC;
signal STARTUP_V6_PWRUP_GTXE1_ML_INSERTED_DINSPI : STD_LOGIC;
signal STARTUP_V6_PWRUP_GTXE1_ML_INSERTED_PREQ : STD_LOGIC;
signal STARTUP_V6_PWRUP_GTXE1_ML_INSERTED_TCKSPI : STD_LOGIC;
signal STARTUP_V6_PWRUP_GTXE1_ML_INSERTED_CFGCLK : STD_LOGIC;
signal GND : STD_LOGIC;
signal VCC : STD_LOGIC;
begin
NlwBlock_float_point_package_module_GND : X_ZERO
port map (
O => GND
);
NlwBlock_float_point_package_module_VCC : X_ONE
port map (
O => VCC
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);

end Structure;

- - - Updated - - -

Pre-synthesis is:

library std;
library IEEE;
library ieee_proposed;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;

use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;

--use IEEE.NUMERIC_STD.ALL;

entity float_point_package_module is
port(
clk : in STD_LOGIC;
enable : in STD_LOGIC;
curr_xV : in float(8 downto -23);--REAL;
xV : in float(8 downto -23);--REAL;
d1 : out float(8 downto -23));
end float_point_package_module;

architecture Behavioral of float_point_package_module is
constant tau : integer := 4;

type array_float_small is array (0 to 6) of float(8 downto -23);
--type array_d1temp is array (0 to 2007) of float(8 downto -23);
type array_float_big is array (0 to 2047) of float(8 downto -23);
type array_float is array (0 to 2007) of float(8 downto -23);

signal read_enable, calc_enable,write_enable : STD_LOGIC := '0';
signal array_curr_xV : array_float_small;
signal array_xV : array_float_big;
-- signal array_d1 : array_float;
--signal endoffile : bit := '0';
-- signal linenumber : integer:=1;

begin
process(clk)
variable i,k,index : integer := 0;
variable d1temp : float(8 downto -23) :=(others=>'0');
variable d1_fixed : array_float :=((others=> (others=>'0')));

file outfile : text is out "./TestFiles/d1_1.txt"; --declare output file
variable outline : line; --line number declaration

begin
if (clk'event and clk = '1') then--or (enable'event and enable = '1') then
if enable = '1' then
read_enable <= '1';
end if;

if read_enable = '1' then
read_enable <= '1';
if(i<=6)then
array_curr_xV(i) <= curr_xV;
end if;
array_xV(i) <= xV;
i := i+1;
if(i = 2048)then
read_enable <= '0';
i := 0;
calc_enable <= '1';
end if;

elsif calc_enable = '1' then
d1temp := (array_curr_xV(k)-array_xV(i+k*tau))*(array_curr_xV(k)-array_xV(i+k*tau));
d1_fixed(i) := d1_fixed(i) + d1temp;
i := i +1;
if(i = 2008 and k < 6)then
i := 0;
k := k+1;
elsif(i=2008 and k=6)then
i := 0;
k := 0;
calc_enable <= '0';
write_enable <= '1';
end if;
elsif write_enable = '1' then
-- for i in 0 to 2007 loop
d1 <= d1_fixed(index);
----------------------------ADDED FOR TEST PURPOSES------------------------
-- if(endoffile='0') then --if the file end is not reached.
-- write(outline, to_real(d1_fixed(index),false,false), right, 10); --to_real for lesbare tall
-- writeline(outfile, outline);
-- linenumber <= linenumber + 1;
-- else
-- null;
-- end if;
-------------------------------END TEST PURPOSES---------------------------
index := index+1;
--end loop;
if(index = 2008)then
index := 0;
write_enable <= '0';
end if;
end if;

end if;
end process;
end Behavioral;

The modulename_synthesis-file has the same entity declaration, but it is 120 075 lines long, so I won't post it here for readability,.

 

[TrickyDicky]

You generally dont get VHDL output from synthesis - are you outputting some VHDL module for post map simulation? What version of XST is it? XST, especially older versions, are pretty poor. Did you use the Xilinx version of the float compatibility library?

I wouldnt use the float package anyway - there is no pipelining so performance will be terrible. Stick with the floating point cores.