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Code VHDL - [expand]
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clkloop:processbeginwhilenot complete loop-- start the loop if complete is not trueclock<= '0';-- assign '0' to clockwaitfor 10ns;-- wait 10 nsclock<= '1';-- now assign '1' to clockwaitfor 10ns;-- again wait for 10 nsendloop;-- if complete is still not true, jump to beginning of the loop and restart, clock will toggle between '0' and '1' with period is 20 ns (50 MHz)wait;-- forever -- if end of loop (complete = true) stop the processendprocess clkloop;