having problem using while loop in vhdl

[Burns111]

clkloop: process
begin
while not complete loop
clock<=0;wait for 10ns;
clock<=1; wait for 10ns;
end loop; 
wait;
end process clkloop;

Can someone please explain this above code to me line by line?

 

[lucbra]

all sites dedicated to VHDL can explain this while loop

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Code VHDL - [expand]
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clkloop: process
begin
   while not complete loop -- start the loop if complete is not true
      clock <= '0';      -- assign '0' to clock
      wait for 10ns;    -- wait 10 ns
      clock <= '1';      -- now assign '1' to clock
      wait for 10ns;   -- again wait for 10 ns
   end loop;             -- if complete is still not true, jump to beginning of the loop and restart, clock will toggle between '0' and '1' with period is 20 ns (50 MHz)
   wait; -- forever     -- if end of loop (complete = true) stop the process
end process clkloop;

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[TrickyDicky]

So what was the problem?