Have Question on verilog

[vcnvcc]

Can you help me understanding this

my_ByteSel = {8’d3, 8’d3}

WIDTH = 8
my_pointer (value) 	 `WIDTH * (value) +: `WIDTH

Wire [10:0] my_counter;

this is what I would like to understand -->

my_counter(my_ByteSel[`my_pointer(i)])
assume that value will take  0 and 1 – only two values.

Thanks..

 

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my_ByteSel = {8’d3, 8’d3}

WIDTH = 8
my_pointer (value) 	 `WIDTH * (value) +: `WIDTH

Wire [10:0] my_counter;

this is what I would like to understand -->

my_counter(my_ByteSel[`my_pointer(i)])
assume that value will take  0 and 1 – only two values.

Thanks..

Where did you get this code snippet from, the code isn't even legal Verilog? Is this something you wrote that you are trying to make work?

The way this is written makes me think that the approach used is based on software concepts and isn't being written with an understanding of hardware.

 

[Mohammed_Verification]

Hi,
Post your specification or the problem clearly. the code seems to be your idea not the synthesizeable one.

 

[raghavkmr]

hey where did u got this ,cant understand the question well