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Has anyone measured what a high impedance pin looks like

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I understand that, when an IC pin is in an High Impedance state, the pin is not connected to anything internal. It will be the voltage whatever it is pulled to outside.

But I am just curious as to whether anyone has measured the value of voltage when the pin is in the high impedance state.

Suppose, for example, say an IC works at 5V. A pin is in a high impedance state at a particular instant. This pin is pulled up to 3.3V since this signal is interfaced with an MCU. Now, let's remove the pull-up to 3.3V on this pin. At this time, anyone can tell me what would be the voltage reading? Just curious to understand this scenario.
 

Hi,

For sure I did this. Especially on faulty parts, or parts that don't work the way I expect them to do.

I do it this way:
* DVM_minus to GND
* DVM_plus to the pin
--> the reading should be close to zero because even if the DVM is rather high impedance it will pull the pin to GND.

But this is is only half the way ... since the PIN could be driven to GND (by programming or by fault ...)

Thus I do the counter measurement:
* DVM_plus to VCC
* DVM_minus to the pin
--> a true high impedance pin will also show about zero Volts. Again the pin gets pulled to VCC, so that the reading (difference to VCC) becomes zero.

This way I can differ between LOW, HIGH and HIGH-Z.

***
If I have many pins to check .. this method is slow.
Then I sped it up*
* DVM_minus to GND
* DVM_plus [100k to GND], [100k to VCC] and to the pin
This way DVM reading tells me:
* 0..0.2V --> pin is driven to GND
* VCC-0.2V ... VCC --> pin is driven to VCC
* close to VCC/2 --> pin is HIGH-Z
* somewhere between 0V and VCC/2 --> pin is PULLED DOWN up by resistor
* somewhere between VCC/2 and VCC --> pin is PULLED UP up by resistor

The value of the resistors should be chosen to get good readings on the expected pull up resistor value. But need to be accurate.
100k+100k give a voltage source of VCC/2 with a source impedance of 50k. This 50k is the value I expect from an AVR internal pull up.
So for a 50k pull up I get a reading of about 3/4 x VCC. The reading is somewhere in the middle between HIGH and HIGH-Z.

To go even further:
Doing measurements on several input pins of the same IC, the voltage readings should be quite equal (for sure with a bit tolerance).
But if you now see one pin voltage that is rather far from the others ... it could be a sign for an ESD damage of the internal pin protection diodes.
(Input pins here are considered HIGH-Z or pulled-up)

Klaus
 

CMOS logic has an input impedance related to the unknown picoamp of leakage current and the input capacitance that depends on the logic family in the order of a few picofarads. Anything you measure with must be significantly higher so even a 10Meg probe will alter the unknown charge.
 

Suppose, for example, say an IC works at 5V. A pin is in a high impedance state at a particular instant. This pin is pulled up to 3.3V since this signal is interfaced with an MCU. Now, let's remove the pull-up to 3.3V on this pin. At this time, anyone can tell me what would be the voltage reading?
Assuming you are measuring with an infinite resistance voltmeter, the reading would be 3.3V due to the small parasitic pin capacitance.
The voltage may then drift higher or lower depending upon the polarity of the small input leakage current from the pin internal CMOS switch.
 

Hi,

the reading would be 3.3V
if we dive that deep into details, then we need to consider the internal Mosfet introduced Q ... which also modifies the voltage.

So to keep it simple:
* floating node voltage is considered undefined ..
* measurement device internal resistance will dominate to pull the node voltage ... so that the reading is close to zero.

(Measurement devices will have internal "load" resistance, otherwise if one (or both) wires are unconnected you get the same effect of reading weird (non zero) voltages. Just the internal resistance makes it show "close to zero". Otherwise the random readings made it rather inconvenient.)

Klaus
 

The act of measuring may change the result, if the pin
impedance is nice and high. You ought to be prepared
to "de-embed" the attributes / contribution of your
instruments.

The high impedance attribute is limited to a range of
operating conditions. "Outside the rails" often engages
some protection diodes. Bidirectional I/Os can be high
Z or low Z depending on state control, and so on.

How high is high, can depend on manufacturer capability
and their perception of "care-abouts". A "digital" pin might
get by with a sloppy 1uA spec even though normal is 1nA
at high temp limit. An analog switch customer might walk
away if a more useful, tighter-to-actual limit isn't spec'd
(somebody else will, if it's within the realm of practical,
because competition).
 

if we dive that deep into details, then we need to consider the internal Mosfet introduced Q ... which also modifies the voltage.
Don't see how that affects the voltage as it's just comes from the fixed capacitance of a static MOSFET (?).
 

Hi,

If the high side MOSFET is ON you surely get VCC, let's say 3.3V.
To make the IO high-Z one needs to switch OFF the high side MOSFET. Means to modify it's V_GS.
A part of the voltage shift at the gate will be capacitively coupled to the output ... thus I expect the output voltage to change a little.

Klaus
 

If by "impedance" you mean both real and complex, the
voltage does modulate the junction and gate capacitances
attached. Diodes and MOS both have strong C-V swings.

Short channel MOSFETs attached as the output portion of
a bidirectional I/O also bring a "leakage balance" element.
 

Hi,

I think it's not essential for the OP's question..
I don't say you are wrong, but I guess you have a different scenario in mind than me.
What worries me:
would be 3.3V due to the small parasitic pin capacitance
Why doesn't it start with a "discharged" capacitance = 0V?

Was the 3.3V actively driven by the pin (internally)? Or externally applied 3.3V?

Is the DVM (with it's own capacitance and resistance) conected all the time? Or just applied for the measurement?

Klaus
 

I understand that, when an IC pin is in an High Impedance state, the pin is not connected to anything internal. It will be the voltage whatever it is pulled to outside.

But I am just curious as to whether anyone has measured the value of voltage when the pin is in the high impedance state.

Suppose, for example, say an IC works at 5V. A pin is in a high impedance state at a particular instant. This pin is pulled up to 3.3V since this signal is interfaced with an MCU. Now, let's remove the pull-up to 3.3V on this pin. At this time, anyone can tell me what would be the voltage reading? Just curious to understand this scenario.

First of all, high impedance state does not mean that it is not connected to anything internally. If you have to assume, the safe bet is that the pin is connected to a gate of a transistor, or to an output of CMOS (e.g. a buffer circuitry where the output pin can be pulled to Vdd by PFET or to Gnd by NFET) where both PFET and NFET are in off state.

When not driven to either Vdd nor Gnd, the voltage on the pin depends on the following:
- capacitance of the pin & traces (even femtofarads matters)
- the last voltage on that capacitance before the pin enters the high impedance state.
- the leakage current of the pin (typically in low nA range)

If the leakage is really small, or you measure the voltage right after the pin enters high-Z, then there's no change in voltage measured because that voltage is being held by the capacitance. This capacitance can be charged or discharged by leakage currents, mainly the leakage between the drain and source of MOSFETs in off state.

After sometime, the capacitance will be fully charged or discharged and when you measure the voltage again, this capacitance voltage is the one that you'll read.
 

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