Hardware IP/UDP stack?

[jdhar]

udp stack

I was wondering if anyone has done or seen a hardware implementation of any ethernet layers greater than the MAC? I was thinking of maybe implementing IP and UDP and hardware, but wasn't sure if anyone had done so already.

Jai

 

[jigdo]

udp fpga

Hello jdhar:


The project is very good.I know some people has use the fpga to realize
the ucos real time OS. Wish you good luck.


Best Regard

jigdo

 

[bibo1978]

udp picoblaze

A router is an example for a layer3 device although not all made in HW, it must include a processing unit, yet MAC can be implemented in HW upper layer control usually is done in software using RTOS sometimes called internetworking OS, some of upper layer function are implemented by hardware to increase the overall speed while others are not "too costly". a Full TCP stack can't be implemented in HW because it would be very costly, sometimes even MAC are implemented with software using DSP, or even a processor because it might cost less.

 

[jdhar]

fpga arp udp

Thanks for the replies. I didn't mean in hardware as in pure hardware - I was referring to FPGA's and programmable logic. I mean, if a MAC can be written in hardware, there's no reason the next layer up could be, right? Right now, I'm using a processor to do all the other layers, but a lot of the stuff is redundant, and can be sped up I imagine (like CRC calculations for example).

 

[luancao]

hardware ip stack

It will a good project if you could implemented it in a single chip. Although maybe most of works are still in software.

Basicly, most Physical layer job could be implemented in hardware. For higher layer, in software. If you have already had a software version. Just make a partition which part will be implemented in hardware, and which part will be implemented in software. And also you should estimate the performance of the implementation. And you should have a CPU core such as MPIS or ARM and OS if possible.

And most important thing is you should design the application as well. How to get it orgized by using the chip you are designing. That's often very tough job for most designer.

 

[CatKing]

udp ip xilinx

some korea company had made it, but i forgot the name, maybe netwiz or else.

 

[layaghi]

picoblaze udp

Hi
The company's Address is:
http://www.wiznet.co.kr/
They has make a Hardware protocol stack called:iinChip W3100A.

Features
- Hardware Internet protocols included:
TCP, IP Ver.4, UDP, ICMP, ARP
- Hardware Ethernet protocols included:
DLC, MAC
- Supports 4 independent connections simultaneously
- Internal ICMP responds to PING commands
- Protocol processing speed: full-duplex 20 Mbps
- Intel MCU bus Interface
- I2C Interface
- Standard MII Interface for under-layer physical chip
- Socket API support for easy application programming
- Supports full-duplex mode
- Internal 16Kbytes Dual-port SRAM for data buffer
- 0.35 µm CMOS technology
- Wide operating voltage:
3.3V internal operation, 5V tolerant 3.3V IOs
- Small 64 Pin LQFP Package

 

[echo47]

stack verilog dual port

A bare-bones UDP interface is actually pretty easy in FPGA. I've been fiddling with doing that on the Xilinx Spartan 3 development board for a hobby project. My FPGA contains a minimal 10 megabit PHY, a MAC, some block RAMs for packet buffering, and a sequencer-assisted PicoBlaze section that helps parse the ARP, ping, and non-fragmented UDP packets that my project needs. (PicoBlaze is a tiny freeware microcontroller written in HDL.) That stuff consumes about 25% of the XC3S200 FPGA, leaving plenty of space for the rest of my project.

It's not done yet, but someday I'll probably share it. It's written in Verilog.

 

[xuruquan]

ip stack fpga

Now we can buy the hardware TCP/IP stack on market , but not cheap!! if the stack can be implemented in CPLD ,thats very good!

 

[elec4fun]

udp in fpga with mii

Hi, look a this site https://www.fpga4fun.com/10BASE-T.html

Hope it will help you....

 

[jdhar]

hardware tcp/ip stack

Hi, look a this site h**p://www.fpga4fun.com/10BASE-T.html

Hope it will help you....

I don't see how this is relevant? The discussion is about stacks implemented in hardware/RTL, not basic layer 1 tx/rx.