There is another shortpoint of more stage: if there is a jump operation, and you need clear up all the pipelines in all the stags, then more cycle will be wasted, compare to less pipeline sta
There is another shortpoint of more stage: if there is a jump operation, and you need clear up all the pipelines in all the stags, then more cycle will be wasted, compare to less pipeline sta
latency? I dont get it, since all operation is done in each stage, so after the 1st flow: means the 1st instructions finished flow through all the stages, then the following instructions should be complete in 1 Clock cycle what? and the clock cycle can be minimize since there is a lot of stages with tiny fractional operation..
Is it your latency refer to the 1st instruction to be completed?
More pipeline stages gets you more complications unless you balance all pipelining stages properly. If all stages aren't properly balanced then throughput of system doesn't increase , it gets decreased. More stages increases time by a signal taken to pass all stages , thus increase in latency.
More pipeline stages gets you more complications unless you balance all pipelining stages properly. If all stages aren't properly balanced then throughput of system doesn't increase , it gets decreased. More stages increases time by a signal taken to pass all stages , thus increase in latency.