Hard do find adc-fifo-usb problem

[Sobakava]

I've a weird problem with my data acquisition board...

Please see the attachment graphic which shows acquired
5000 samples. There are some spikes (seems periodic) at
the sampled signal... Deviation of spikes from original
signal is 256,512,768 digits...

This signal generated by a function generator, approximately
1kHz period... I increased and decreased period, same problem
exists

Signal sampled with an 12bit 25MSPS ADC, then it passed to FIFO,
then I transferred it to PC...

Now I don't know what is happening, there is something wrong at one of these stages:

-Sampling by ADC
-Writing digitized 12bit data to FIFO
-Reading stored data from FIFO
-Transferring data to PC


System gets ~5000 samples continuosly and writes to FIFO, then, when PC wants to read, it reads and sends FIFO contents....

It is an interesting engineering problem, please tell me what would you check first to "find source of problem" ?

Regards

 

[pisoiu]

Hi,
It maight be possible that in your system appers problems like ground-bouncing and switching noise. Do you use 4 layer board (2 signals, 1 gnd plane and 1 power plane)? Your components are decoupled in the nearby with appropriate capacitors (self resonant frequency higher than knee frequency)? Do you use separately analog and digital circuits (this is mandatory in ADC systems) ? If you can, PM me the pcb, I'll take a look at it (protel or orcad).

 

[Sobakava]

Sampling frequency is not so high (<5/10 MHz), I tried 3MHz also, input signal is a few kHz...
I suppose by-pass caps are placed well/enough. Unfortunately this is not a multi layer board, it is two sided hole plated PCB and I covered with GND both bottom and top layer...

 

[llrry]

Since you can not check ADC converted data directly, first check from PC interface and appraoching the ADC step by step as you listed.

 

[pisoiu]

Hi,
Usually, adc systems are very strict about analog and digital circuits separation. All analog circuits must be powered together with analog vcc and analog gnd, and digital circuits - the same - digital vcc and digital gnd. At one single point, these both analog and digital power wires must be tied together. If you tied together all vcc-s and all gnd-s regardless if they are analog or digital, my opinion is that there is nothing you can do. The noise is not given by sampling frequency, which may vary, it is given by frequency related to transition times of the digital signals, which is relatively constant for each family of logic devices.

 

[Sobakava]

I think such a bad grounding would cause noise in signal but I think my problem is some spikes which is affecting 1-2 significiant bits... (bit8, bit9 etc)

 

[Sobakava]

I use AD0801U A/D converter and CY7205 25ns FIFO. ADC clock and FIFO write clock generated by my CPLD from same input clock. If there is some bad alignment of the edges of ADC and FIFO clocks, this phase error can be summed and make errors in some definite point then I can be recovered itself after phase turn...
This is a possibility but I can't understand is it possible while the clocks generated from same source...
This is the only problem with my system now, if I find the SOURCE of THE PROBLEM, I'll try to fix it...

thanx for your help,

still waiting for recommendations and opinions...

 

[manitooo]

it could depend of the propagation time of all your data bits... In fact, when a byte is establishing itself in front of your fifo, it is synchronous to the sampling frequency... but you have a delay for the propagation of the converted value along the tracks... you should insert a delay for the FIFO clock or/and try to shorten your data bit tracks in your PCB...

Something you could try is to have exactly the same length for all your data bit track between ADC and FIFO..

Moreover, try to look the sampled data with a scope to have an idea of the slew rate of the edges... it could be possible that you have a capacitor parasite that makes your edges quiet round and to slow to be trigged at the good time....