Handling strings in verilog

[a_k_s]

Hi,

I am new to verilog coding. I have a problem in handling strings.
In my implementation I will receive a parameter value from DSP to my FPGA as 32'd58710000, I have to convert each digit to ASCII and send to another module.
like 5 = 35 in ascii
8 = 38 in ascii and so on.
My problem how do i extract each digit.

 

[FvM]

More exactly speaking, you are asking for binary to decimal conversion methods. You can consider e.g. https://en.wikipedia.org/wiki/Double_dabble

 

[a_k_s]

More exactly speaking, you are asking for binary to decimal conversion methods. You can consider e.g. https://en.wikipedia.org/wiki/Double_dabble

Hi Fvm,

ya i was talking about the same thing. I got a code regarding the same.

module add3(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @ (in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule


module binary_to_BCD(A,ONES,TENS,HUNDREDS);
input [7:0] A;
output [3:0] ONES, TENS;
output [1:0] HUNDREDS;
wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,A[7:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};
add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);
assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};
assign HUNDREDS = {c6[3],c7[3]};
endmodule


the same code i converted to task so that i can reuse it. But in simulation i am not able to get the correct value after converting to tasks.

module task_test(i_value,O_ONES,O_TENS,O_HUNDREDS);
input [7:0] i_value;
output [3:0] O_ONES, O_TENS;
output [1:0] O_HUNDREDS;

reg [3:0] O_ONES, O_TENS;
reg [1:0] O_HUNDREDS;
always @ (i_value)
begin
binary_to_BCD(i_value,O_ONES,O_TENS,O_HUNDREDS);
end
task add3/*(in,out)*/;
input [3:0] in;
output [3:0] out;
reg [3:0] out;
// always @ (in)
begin
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
$display("Reset TASK add3 COMPLETE");
end
endtask

task binary_to_BCD;
input [7:0] A;
output [3:0] ONES, TENS;
output [1:0] HUNDREDS;
reg [3:0] c1,c2,c3,c4,c5,c6,c7;
reg [3:0] d1,d2,d3,d4,d5,d6,d7;

begin
c1<=4'b0000;
c2<=4'b0000;
c3<=4'b0000;
c4<=4'b0000;
c5<=4'b0000;
c6<=4'b0000;
c7<=4'b0000;

assign d1 = {1'b0,A[7:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};


add3(d1,c1);
add3(d2,c2);
add3(d3,c3);
add3(d4,c4);
add3(d5,c5);
add3(d6,c6);
add3(d7,c7);
assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};
assign HUNDREDS = {c6[3],c7[3]};
endtask
endmodule

can you let me know whats the mistake