chandhramohan
Member level 2
clock out pll out
Hi,
Im doing gate level timing simulation. Im getting in glitch in PLL clock out, which translates as X (during glitch period), when it passes through clock tree buffers, this clk with glitch goes to CLK Divider flop ( no timing chk is added to clk divider flops), but still Flop output is giving X as result of glitch.
The design is in Tapeout stage.
1. In real time does it affect functional operation bcoz of small glitch in clock ?
2. Is it a normal one and can be avoided in timing simulation by adding any sdf compile switch ?
Thanks a lot for your response.
Regards
Chandra
Hi,
Im doing gate level timing simulation. Im getting in glitch in PLL clock out, which translates as X (during glitch period), when it passes through clock tree buffers, this clk with glitch goes to CLK Divider flop ( no timing chk is added to clk divider flops), but still Flop output is giving X as result of glitch.
The design is in Tapeout stage.
1. In real time does it affect functional operation bcoz of small glitch in clock ?
2. Is it a normal one and can be avoided in timing simulation by adding any sdf compile switch ?
Thanks a lot for your response.
Regards
Chandra