SystemC is more than VHDL. It includes RTL semantics with C syntax, and thus it may replace VHDL. However, this will not be a methodology shift. Instead of writing "while clk'event and clk=1" we can write "sensitive_pos(clk)". The methodology will be the same. Where SystemC is strong is system level design (above RTL). At this level we will be able to describe with a common language a lot of different components (hardware, RTOS, application software, device drivers, communication interfaces, e.t.c). We will also be able to perform different refinement steps in all these component types. This will be a methodology shift and this is what SystemC is promising.