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Handel-C and SystemC: could they kill VHDL and Verilog?

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mart242

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handel-c or vhdl

What's your tought on Handel-C and SystemC versus VHDL and Verilog? Do you think they could make VHDL and Verilog disappear?

Me, I think that because of languages like that, software engineers might decide that they "know how to do ASICs and FPGAs" simply because they could design them with a language that looks like C and C++.

Don't get me wrong, languages like that are usefull for validating algorythms and quick prototyping, but you still need to have a strong hardware knowledge. So while managers might think that software engineers could do our a job, I don't think it will ever be the case...
 

nitr8

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handel-c

u must be joking me.
Accellera has already decided for systemverilog to be the next HDL standard. synopsys has also donated some of systemc stuff to them as well.

after vhdl and verilog merged to form accellera. a new war started between superlog and systemc. both were fighting to be the next standard for system level design. but accellera decided otherwise and came up with systemverilog as a standard. co design automation then donated there extensible sysnthsizable code to them and as far as i know systemverilog 3.1 is a subset of superlog. seeing this synopsys also decided to donated stuff to them, these donations from synopsys will be added to systemverilog 3.2 which is supposed to be released in june 2003.

So in essence systemverilog will have the best of both worlds.
 

mami_hacky

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handel c to verilog

Dear nitr, would you please give some useful links to this new systemverilog. For me it was the first time to hear it. Really, systemC will disappear, and system verilog will get it's place?
 

satya

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verilog vhdl systemc future

Hi,
can u please give me a link where I can get the HANDEL-C standard or any books on it.I m looking for it for quite long time...

Thanks in advance,
Regards,
- satya
 

leon

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system c, system verilog or handel-c

Just as the conclusion in this paper, I think that it will need about 5-10 years that the high-level hdl can replace the vhdl/verilog.
 

Rus

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It seems like vhdl/verilog may dissapear from market in near future (10 years for ex)
 

geconom

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SystemC is more than VHDL. It includes RTL semantics with C syntax, and thus it may replace VHDL. However, this will not be a methodology shift. Instead of writing "while clk'event and clk=1" we can write "sensitive_pos(clk)". The methodology will be the same. Where SystemC is strong is system level design (above RTL). At this level we will be able to describe with a common language a lot of different components (hardware, RTOS, application software, device drivers, communication interfaces, e.t.c). We will also be able to perform different refinement steps in all these component types. This will be a methodology shift and this is what SystemC is promising.
 

semicon

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Rus said:
It seems like vhdl/verilog may dissapear from market in near future (10 years for ex)
i don't think so.
 

cmfan

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I think systemc has its ability and advantage in high level modeling and functional verification, especially the system level. It can't replace verilog and vhdl in circuit implementation because its low efficiency when it is compiled to RTL.
 

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