Hi Guys
I want to intergrate PLL layout thus i have some questions regarding it.
Pll is having digital as well as analog blocks and the digital is working in high frequency in the range of Giga Hz. So can you pls tell wht all guidlines i should follow while intergrating these blocks in layout. The technology is 90nano and as everybody is aware that 90nano has a huge leakage factor.
thus can anyone pls tell wht all guidlines or tips should be followed while doing layout intergartion of blocks like these.
Ensure the digital signal line don't cross the analog line. If needed, ensure it is properly shield with ground plane. Or else you may see spur, which is cause by your reference frequency of the PLL on your VCO output. The best is separate the analog power line for different circuit as well. Star connected it only at the pad.