Guidelines on how to code a pipelined processor in HDL

[hannibal2469]

Hi,

I am planning on doing a project, implementing a MIPS 32 bit pipelined processor in SystemVerilog, I have never done a big project in hdl, all the code that I have written till now has been for very small modules. I need some guidelines on how to proceed with this, I have noone to ask for help, and I am a little scared since it is a very big project(at least w.r.t my current experience), any tips or guidelines on how to approach this will be very helpful.

Thanks In advance

 

[hannibal2469]

I will be doing the MIPS processor described in hennessy and patterson, the datapath, the control unit and the external memory, I think this is feasible, please let me know if this sounds too out of my league.

 

[dpaul]

I will be doing the MIPS processor described in hennessy and patterson, the datapath, the control unit and the external memory, I think this is feasible, please let me know if this sounds too out of my league.

You are the best person to make this judgement, since none of us here knows about your skill sets and expertise. This forum can help help you whenever you have specific problems.
There are also many 32bit MIPS projects done in OpenCores. I don't know how relevant they are in respect what you want to do, but I guess you can take some initial ideas from a project there.