Guidelines for defining the False path in a design

[vipulsinha]

Hi All

I am wondering as what considerations one must take to declare the path as False path. We know that the paths between two different clocks/Clock groups are freated as false path ans is not considered in the STA analysis.

Anyone has some guideline for defining the False path in the design .

Thanks

Vipul

 

[ljxpjpjljx]

Re: False Path

cross-domain signals and some signals which should not be considered!

 

[feel_on_on]

False Path

false path means some path U need not think about their timing .

 

[eChipDesign]

Re: False Path

For any signal which enters a particular clock domain, timing check is done and error is reported if timing is not met. But some of these signals from design perspective you know that wouldnt affect your timeing. (For eg static register signals which are stable immediately after reset)

The differentiation of false path signals can be done only by design engineers and not by back end people. Once a timing violation has been reported it is the duty of the design engineer to analyze the path and come to a decision if the signal transition will create timing issues in the cross over domain.

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eChipDesign

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[owen_li]

Re: False Path

I think you should communicate with the logic designer.
They know which clock domains can be set false path!
thanks!

 

[D Saurabh]

False Path

another possible false path is the path to the input of any synchronizers. For eg if u r using a 2 FF reset synchronizer to synchronize the deassertion of the reset in ur design, then the async path to the reset pin of the synchronizer FF can be set to false. Only paths from the output of the synchronizer to reset pins of other FF in the design are true paths.

 

[vlsichipdesigner]

Re: False Path

hi,

my 2 cents,

simple definition is wanted timing paths.
Few examples of false path could be

* paths which cross clocks, and for which you already have synchronizers.
* paths which cross functional domains like Functional domain and scan domains which are not valid timing paths.
* paths with in the functional domain, but across two functional domains like transmit path and recieve paths.

For some diagramatic explanation visit
https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/statictiminganalysis.html

myprayers,
chip design made easy
https://www.vlsichipdesign.com