guard ring contacts for the PMOS transistors

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Junus2012

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Dear friends,

I usually connect the NWELL substrate contact for the PMOS transistors by putting the NWELL contact only on the right and lift, I am not making it as closed ring as the name indicate. by any way I am verifying that I have no latchup problem

Also please I have a question, is it good idea to put Substrate contact (GND) beside the PMOS transistors well to make it more reveresed biased

Thank you very much
 

I try to fully enclose the tap on the nwell to further reduce the risk of matchup. But if you’re not seeing violations, you might be okay for now. Once you connect to io at top level, you might get latchup violations for having active devices connected to io without a fully enclosed guard ring. Or even violations because those open guard rings are too close to active diffusion contacting io.

As far as contacting the substrate, it’s a good idea to surround it completely to get a good contact to the substrate.
 

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