I created a test bench for tra.vhdl (tra_test.vhdl):
--
-- tra_test.vhdl, test bench for tra.vhdl
--
-- supplies clock and reset
--
--
library ieee;
use ieee.std_logic_1164.all;
entity tra_test is
end;
architecture test of tra_test is
signal q: std_logic_vector (2 downto 0);
signal clk: std_logic;
signal rst: std_logic;
component tra is
port (
rst: in std_logic;
clk: in std_logic;
q: out std_logic_vector (2 downto 0)
);
end component;
begin
RESET: -- negative true reset despite name
process
begin
if rst /= '0' then
rst <= '0';
end if;
wait for 22 ns;
rst <= '1';
wait;
end process;
CLOCK:
process
begin
if clk /= '0' then
clk <= '0';
end if;
wait for 10 ns;
clk <= not clk;
end process;
TRATEST:
component tra
port map (
rst => rst,
clk => clk,
q => q
);
end;
--
Once tra.vhdl (your original vhdl) has been analyzed, analyze tra_test.vhdl:
ghdl -a tra_test.vhdl
Then run it:
ghdl -r tra_test --vcd=tra.vcd --stop-time=110ns
Then run gtkwave
gtkwave tra.vcd tra.sav
The optional save file tra.sav:
[timestart] 0
[size] 1000 600
[pos] 195 2
*-24.992649 9100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@28
clk
@29
q[2:0]
@28
rst
[pattern_trace] 1
[pattern_trace] 0
--
You could also use ghdl's native wave form format:
ghdl -r tra_test --stop-time=110ns --wave=tra_testbench.ghw
and display it with gtkwave:
gtkwave tra_testbench.ghw tra_testbench.sav
where tra_testbench.sav contains:
[timestart] 0
[size] 1000 600
[pos] 195 2
*-24.992649 9100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tra_test.
[treeopen] top.tra_test.tratest.
@28
top.tra_test.tratest.clk
top.tra_test.tratest.rst
@29
#{top.tra_test.tratest.q[2:0]} top.tra_test.tratest.q[2] top.tra_test.tratest.q[1] top.tra_test.tratest.q[0]
[pattern_trace] 1
[pattern_trace] 0
--
And you can of course setup your own save files in gtkwave by leaving off tra.sav or tra_testbench.sav on the gtkwave command line.