For purposes of not contaminating the on chip analog
ground by digital section current spikes against bond
wire and lead frame inductance. Tying them off-chip is
better than tying them on-chip. Let the digital section's
ground bounce around by 100mV, who cares? Let the
ADC ground bounce the same, when you're looking for
1mV LSB settling in 100nS, you're pretty well screwed.
A digital section with a common clock can easily pull
100mA peak current. Way worse, if you have tens of
CMOS outputs looking at tens of pF of load apiece and
slapping them at nS risetimes with their 25mA drive
current. But anyway, say 100mA current impulse is 1nS
up, 1nS down, no flat top. Say your bond wire is 1mm,
so about 1nH, you have L*dI/dt of 1E-9*(100mA/1E-9) -
100mV of on-chip ground bounce.
All reasonable-ish IC numbers. Best keep that bit o'
nasty to yourself, Mr. Digital Section. Blow it out
your own pipe, not mine, says Mr. Prancey Analog.
Of course making the ground that serves both, stay
clean is now on you. But you have resources (like
thick copper ground plane, high value low ESR caps
and routing freedom) that the IC (with its spindly little
legs and even thinner wire bonds, if it's not a bumped
chip-scale package) does not.