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[SOLVED] gpdk 90 layout error(metal width should be > 0.07u

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arya.jagadeesh

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i imported design by layout xl(generate from source)

it is showing drc error at all the metal contacts at sources and drains of transistors like metal width should be>0.07 and area should be >0.12um2
these are there in drm of gpdk90....still here i am not changing any thing it is automatically generated from source....how to correct it

thanks
 

And was this design sourced from the same PDK or
following that rules set? You say nothing about the
actual dimensions at the flagged sites and these
might easily be valid errors (of expectation?).
 

it is sourced from same pdk....

then transistors are coming directly after gen from source in layout xl........
then error at metal contact at source and drain.....metal contac(implant to metal)....is giving error ...here they are coming and i am not changing any thing .....how to fix this...

and also how to avoid grid error

thanks
 

And you still say nothing about the actual dimensions.
There's no use instructing you until you can be clear
about the real problem. Blaming the transistors or the
PDK or the rules or whatever is losing behavior. Be
proactive and do some debugging. It builds character.
 

The rules you originally mention, seem like:

- Met1 dimension ought to pass, it is greater than rule of 0.07
- Met1 area limit value seems insane, a ~0.12 x ~0.24um
metal is 0.0288 um2 and 0.12um needs 0.3 x 0.4um, way
out of line with the purported geometry of the process.

Your units question earlier bears some checking. So does the
validity of any given gpdk rule, against the source and target
foundries' corresponding design rule, and the source and
streamed-in dimensions (user units vs database units is
always there for you to screw up). Until you can say
where the discrepancy, if any, comes in you are not in
a position to trust any tool or data. Check it all. Check it
twice. Even, or especially, the boring trivial stuff you'd
like to believe in without having to.
 
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